这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F205ZET6-GD32 ARM Cortex-M3 Microcontroller

兆易创新GD32F205ZET6-GD32 ARM Cortex-M3 Microcontroller GigaDevice Semiconductor Inc. GD32F205xx ARM® Cortex®-M3 32-bit MCU Datasheet General description The GD32F205xx device belongs to the performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best cost-performance ratio in terms of processing capacity, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F205xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, a USBFS. Additional peripherals as TFT-LCD Interface (TLI) and EXMC interface with SDRAM extension support are included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F205xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, automotive navigation and so on. Device information Table 2-1. GD32F205xx devices features and peripheral list   Part Number GD32F205xx   RC RE RG RK VC VE VG VK Flash Fast area (KB) 256 512 384 384 256 512 384 384   Normal area (KB) 0 0 640 2688 0 0 640 2688   Total (KB) 256 512 1024 3072 256 512 1024 3072 SRAM (KB) 128 128 256 256 128 128 256 256 Timers General timer (16-bit) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13)   Advanced timer (16-bit) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7)   SysTick 1 1 1 1 1 1 1 1   Basic timer (16- bit) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6)   Watchdog 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 Connectivity USART 4 4 4 4 4 4 4 4     UART 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 4 (3-4,6-7) 4 (3-4,6-7) 4 (3-4,6-7) 4 (3-4,6-7)   I2C 3 3 3 3 3 3 3 3     SPI/I2S 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2)   SDIO 1 1 1 1 1 1 1 1
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F205ZET6-GD32 ARM Cortex-M3 Microcontroller

GigaDevice Semiconductor Inc.
GD32F205xx
ARM® Cortex®-M3 32-bit MCU
Datasheet

General description

The GD32F205xx device belongs to the performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best cost-performance ratio in terms of processing capacity, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F205xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, a USBFS. Additional peripherals as TFT-LCD Interface (TLI) and EXMC interface with SDRAM extension support are included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications.
The above features make GD32F205xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, automotive navigation and so on.

Device information

Table 2-1. GD32F205xx devices features and peripheral list

 

Part Number

GD32F205xx

 

RC

RE

RG

RK

VC

VE

VG

VK

Flash

Fast area (KB)

256

512

384

384

256

512

384

384

 

Normal area (KB)

0

0

640

2688

0

0

640

2688

 

Total (KB)

256

512

1024

3072

256

512

1024

3072

SRAM (KB)

128

128

256

256

128

128

256

256

Timers

General timer

(16-bit)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

 

Advanced timer

(16-bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

1

1

1

1

 

Basic timer (16-

bit)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

 

Watchdog

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

Connectivity

USART

4

4

4

4

4

4

4

4

 

 

UART

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

4

(3-4,6-7)

4

(3-4,6-7)

4

(3-4,6-7)

4

(3-4,6-7)

 

I2C

3

3

3

3

3

3

3

3

 

 

SPI/I2S

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

 

SDIO

1

1

1

1

1

1

1

1

 

CAN

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

 

TLI

0

0

0

0

1

1

1

1

GPIO

51

51

51

51

82

82

82

82

EXMC/SDRAM

0/0

0/0

0/0

0/0

1/0

1/0

1/0

1/0

ADC (CHs)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

DAC

2

2

2

2

2

2

2

2

 

 

Part Number

GD32F205xx

 

ZC

ZE

ZG

ZK

Flash

Code area (KB)

256

512

384

384

 

Data area (KB)

0

0

640

2688

 

Total (KB)

256

512

1024

3072

SRAM (KB)

128

128

256

256

Timers

General timer (16-

bit)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

 

Advanced timer

(16-bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

 

Basic timer (16-

bit)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

 

Watchdog(16-bit)

2

2

2

2

 

RTC

1

1

1

1

Connectivity

USART

4

4

4

4

 

UART

4

4

4

4

 

I2C

3

3

3

3

 

 

SPI/I2S

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

 

SDIO

1

1

1

1

 

CAN

2

2

2

2

 

USBFS

1

1

1

1

 

TLI

1

1

1

1

GPIO

114

114

114

114

EXMC/SDRAM

1/1

1/1

1/1

1/1

ADC (CHs)

3(24)

3(24)

3(24)

3(24)

DAC

2

2

2

2

Package

LQFP144

 

Memory map

Table 2-2 GD32F205xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

External Device

 

 

 

AHB

0xC000 0000 - 0xDFFF FFFF

EXMC - SDRAM

 

 

0xA000 1000 - 0xBFFF FFFF

Reserved

 

 

0xA000 0000 - 0xA000 0FFF

EXMC - SWREG

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC - NOR/PSRAM/SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

AHB2

0x5004 0000 - 0x5FFF FFFF

Reserved

 

 

 

 

 

 

 

AHB1

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4002 3400 - 0x4FFF FFFF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1400 - 0x4002 1FFF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0800 - 0x4002 0FFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA0

 

 

0x4002 0000 - 0x4002 03FF

DMA1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 8400 - 0x4001 FFFF

Reserved

 

 

0x4001 8000 - 0x4001 83FF

SDIO

 

 

0x4001 7800 - 0x4001 7FFF

Reserved

 

 

0x4001 7400 - 0x4001 77FF

GPIOH

 

 

0x4001 7000 - 0x4001 73FF

USART5

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

TLI

 

 

0x4001 5800 - 0x4001 67FF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

TIMER10

 

 

0x4001 5000 - 0x4001 53FF

TIMER9

 

 

0x4001 4C00 - 0x4001 4FFF

TIMER8

 

 

0x4001 4000 - 0x4001 4BFF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

ADC2

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 C400 - 0x4000 FFFF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

I2C2

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

UART7

 

 

0x4000 7800 - 0x4000 7BFF

UART6

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 5C00 - 0x4000 63FF

USBFS/CAN shared

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

SRAM

 

 

AHB

0x2004 0000 - 0x3FFF FFFF

Reserved

 

 

0x2002 0000 - 0x2003 FFFF

SRAM2(128KB)

 

 

0x2001 C000 - 0x2001 FFFF

SRAM1(16KB)

 

 

0x2000 0000 - 0x2001 BFFF

SRAM0(112KB)

 

 

 

 

 

Code

 

 

 

 

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF B000 - 0x1FFF F7FF

System memory

 

 

0x0830 0000 - 0x1FFF AFFF

Reserved

 

 

0x0800 0000 - 0x082F FFFF

Main flash(3072KB)

 

 

 

0x0000 0000 - 0x07FF FFFF

Aliased to flash or system memory according to BOOT

pins configuration

 

GD32F205Zx LQFP144 pin definitions


Table 2-3. GD32F205Zx LQFP144 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4 Alternate:TRACED1, EXMC_A20

Remap: TLI_B0

 

PE5

 

4

 

I/O

 

5VT

Default: PE5

Alternate:TRACED2, EXMC_A21 Remap: TIMER8_CH0, TLI_G0

 

PE6

 

5

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3, EXMC_A22 Remap: TIMER8_CH1, TLI_G1

VBAT

6

P

 

Default: VBAT

PC13-

TAMPER- RTC

 

7

 

I/O

 

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

 

8

 

I/O

 

Default: PC14 Alternate: OSC32IN

PC15- OSC32OUT

 

9

 

I/O

 

Default: PC15 Alternate: OSC32OUT

 

PF0

 

10

 

I/O

 

5VT

Default: PF0

Alternate: EXMC_A0 Remap: I2C1_SDA

 

PF1

 

11

 

I/O

 

5VT

Default: PF1

Alternate: EXMC_A1 Remap: I2C1_SCL

 

PF2

 

12

 

I/O

 

5VT

Default: PF2

Alternate: EXMC_A2 Remap: I2C1_SMBA

 

PF3

 

13

 

I/O

 

5VT

Default: PF3

Alternate: EXMC_A3, ADC2_IN9

 

PF4

 

14

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4, ADC2_IN14

 

PF5

 

15

 

I/O

 

5VT

Default: PF5

Alternate: EXMC_A5, ADC2_IN15

VSS_5

16

P

 

Default: VSS_5

VDD_5

17

P

 

Default: VDD_5

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PF6

PF6

18

I/O

 

Alternate: ADC2_IN4, EXMC_NIORD

 

 

 

 

Remap: TIMER9_CH0, UART6_RX

 

 

 

 

Default: PF7

PF7

19

I/O

 

Alternate: ADC2_IN5, EXMC_NREG

 

 

 

 

Remap: TIMER10_CH0, UART6_TX

 

 

 

 

Default: PF8

PF8

20

I/O

 

Alternate: ADC2_IN6, EXMC_NIOWR

 

 

 

 

Remap: TIMER12_CH0

 

 

 

 

Default: PF9

PF9

21

I/O

 

Alternate: ADC2_IN7, EXMC_CD

 

 

 

 

Remap: TIMER13_CH0

 

 

 

 

Default: PF10

PF10

22

I/O

 

Alternate: ADC2_IN8, EXMC_INTR

 

 

 

 

Remap: TLI_DE

 

OSCIN

 

23

 

I

 

Default: OSCIN

Remap: PH0

 

OSCOUT

 

24

 

O

 

Default: OSCOUT

Remap: PH1

NRST

25

I/O

 

Default: NRST

 

 

 

 

Default: PC0

PC0

26

I/O

 

Alternate: ADC012_IN10

 

 

 

 

Remap: EXMC_SDNWE

 

PC1

 

27

 

I/O

 

Default: PC1

Alternate: ADC012_IN11

 

 

 

 

Default: PC2

PC2

28

I/O

 

Alternate: ADC012_IN12

 

 

 

 

Remap: EXMC_SDNE0, SPI1_MISO

 

 

 

 

Default: PC3

PC3

29

I/O

 

Alternate: ADC012_IN13

 

 

 

 

Remap: EXMC_SDCKE0, SPI1_MOSI, I2S1_SD

VSSA

30

P

 

Default: VSSA

VREF-

31

P

 

Default: VREF-

VREF+

32

P

 

Default: VREF+

VDDA

33

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

34

I/O

 

Alternate: WKUP, USART1_CTS, ADC012_IN0,

TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI

 

 

 

 

Remap: UART3_TX

 

 

 

 

Default: PA1

PA1

35

I/O

 

Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1,

TIMER4_CH1

 

 

 

 

Remap: UART3_RX

 

PA2

 

36

 

I/O

 

Default: PA2

Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2,

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

TIMER4_CH2, TIMER8_CH0, SPI0_IO3

 

 

 

 

Default: PA3

PA3

37

I/O

 

Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3,

TIMER4_CH3, TIMER8_CH1, SPI0_IO4

 

 

 

 

Remap: TLI_B5

VSS_4

38

P

 

Default: VSS_4

VDD_4

39

P

 

Default: VDD_4

 

 

 

 

Default: PA4

PA4

40

I/O

 

Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,

ADC01_IN4

 

 

 

 

Remap: SPI2_NSS, I2S2_WS, TLI_VSYNC

 

 

 

 

Default: PA5

PA5

41

I/O

 

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

 

 

 

 

Remap: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON

 

 

 

 

Default: PA6

PA6

42

I/O

 

Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,

TIMER7_BRKIN, TIMER12_CH0

 

 

 

 

Remap: TIMER0_BRKIN, TLI_G2

 

 

 

 

Default: PA7

PA7

43

I/O

 

Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,

TIMER7_CH0_ON, TIMER13_CH0

 

 

 

 

Remap: TIMER0_CH0_ON

 

PC4

 

44

 

I/O

 

Default: PC4

Alternate: ADC01_IN14

 

PC5

 

45

 

I/O

 

Default: PC5

Alternate: ADC01_IN15

 

 

 

 

Default: PB0

PB0

46

I/O

 

Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON

 

 

 

 

Remap: TIMER0_CH1_ON, TLI_R3

 

 

 

 

Default: PB1

PB1

47

I/O

 

Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON

 

 

 

 

Remap: TIMER0_CH2_ON, TLI_R6

PB2

48

I/O

5VT

Default: PB2, BOOT1

 

PF11

 

49

 

I/O

 

5VT

Default: PF11

Alternate: EXMC_NIOS16, EXMC_SDNRAS

 

PF12

 

50

 

I/O

 

5VT

Default: PF12

Alternate: EXMC_A6

VSS_6

51

P

 

Default: VSS_6

VDD_6

52

P

 

Default: VDD_6

 

PF13

 

53

 

I/O

 

5VT

Default: PF13

Alternate: EXMC_A7

 

PF14

 

54

 

I/O

 

5VT

Default: PF14

Alternate: EXMC_A8

 

PF15

 

55

 

I/O

 

5VT

Default: PF15

Alternate: EXMC_A9

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PG0

 

56

 

I/O

 

5VT

Default: PG0

Alternate: EXMC_A10

 

PG1

 

57

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11

 

PE7

 

58

 

I/O

 

5VT

Default: PE7

Alternate: EXMC_D4, UART6_RX Remap: TIMER0_ETI

 

PE8

 

59

 

I/O

 

5VT

Default: PE8

Alternate: EXMC_D5, UART6_TX Remap: TIMER0_CH0_ON

 

PE9

 

60

 

I/O

 

5VT

Default: PE9

Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

61

P

 

Default: VSS_7

VDD_7

62

P

 

Default: VDD_7

 

PE10

 

63

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

PE11

 

64

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8

Remap: TIMER0_CH1, TLI_G3

 

PE12

 

65

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON, TLI_B4

 

PE13

 

66

 

I/O

 

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2, TLI_DE

 

PE14

 

67

 

I/O

 

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3, TLI_PIXCLK

 

PE15

 

68

 

I/O

 

5VT

Default: PE15 Alternate: EXMC_D12

Remap: TIMER0_BRKIN, TLI_R7

 

PB10

 

69

 

I/O

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX

Remap: TIMER1_CH2, TLI_G4, SPI1_SCK, I2S1_CK

 

PB11

 

70

 

I/O

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3, TLI_G5

VSS_1

71

P

 

Default: VSS_1

VDD_1

72

P

 

Default: VDD_1

 

PB12

 

73

 

I/O

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS, CAN1_RX

PB13

74

I/O

5VT

Default: PB13

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON,

I2S1_CK, CAN1_TX

 

PB14

 

75

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0

 

PB15

 

76

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1

 

PD8

 

77

 

I/O

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX

 

PD9

 

78

 

I/O

 

5VT

Default: PD9

Alternate: EXMC_D14 Remap: USART2_RX

 

PD10

 

79

 

I/O

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, TLI_B3

 

PD11

 

80

 

I/O

 

5VT

Default: PD11 Alternate: EXMC_A16

Remap: USART2_CTS

 

PD12

 

81

 

I/O

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS

 

PD13

 

82

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18

Remap: TIMER3_CH1

VSS_8

83

P

 

Default: VSS_8

VDD_8

84

P

 

Default: VDD_8

 

PD14

 

85

 

I/O

 

5VT

Default: PD14

Alternate: EXMC_D0 Remap: TIMER3_CH2

 

PD15

 

86

 

I/O

 

5VT

Default: PD15

Alternate: EXMC_D1 Remap: TIMER3_CH3

 

PG2

 

87

 

I/O

 

5VT

Default: PG2

Alternate: EXMC_A12

 

PG3

 

88

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13

 

PG4

 

89

 

I/O

 

5VT

Default: PG4

Alternate: EXMC_A14, EXMC_BA0

 

PG5

 

90

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15, EXMC_BA1

 

PG6

 

91

 

I/O

 

5VT

Default: PG6

Alternate: EXMC_INT1 Remap:TLI_R7

PG7

92

I/O

5VT

Default: PG7

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: EXMC_INT2

Remap: USART5_CK, TLI_PIXCLK

 

PG8

 

93

 

I/O

 

5VT

Default: PG8

Alternate: EXMC_SDCLK, USART5_RTS

VSS_9

94

P

 

Default: VSS_9

VDD_9

95

P

 

Default: VDD_9

 

 

PC6

 

 

96

 

 

I/O

 

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6, USART5_TX

Remap: TIMER2_CH0, TLI_HSYNC

 

 

PC7

 

 

97

 

 

I/O

 

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7, USART5_RX

Remap: TIMER2_CH1, TLI_G6

 

PC8

 

98

 

I/O

 

5VT

Default: PC8

Alternate: TIMER7_CH2, SDIO_D0, USART5_CK

Remap: TIMER2_CH2

 

PC9

 

99

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3, SDIO_D, CK_OUT1 Remap: TIMER2_CH3, I2C2_SDA

 

 

PA8

 

 

100

 

 

I/O

 

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF

Remap: TLI_R6, I2C2_SCL

 

PA9

 

101

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

Remap: I2C2_SMBAI

 

PA10

 

102

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

 

 

PA11

 

 

103

 

 

I/O

 

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

Remap: TLI_R4

 

 

PA12

 

 

104

 

 

I/O

 

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

Remap: TLI_R5

 

PA13

 

105

 

I/O

 

5VT

Default: JTMS, SWDIO

Remap: PA13

NC

106

 

 

-

VSS_2

107

P

 

Default: VSS_2

VDD_2

108

P

 

Default: VDD_2

 

PA14

 

109

 

I/O

 

5VT

Default: JTCK, SWCLK

Remap: PA14

PA15

110

I/O

5VT

Default: JTDI

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

111

 

I/O

 

5VT

Default: PC10

Alternate: UART3_TX, SDIO_D2

Remap: USART2_TX, SPI2_SCK, I2S2_CK, TLI_R2

 

PC11

 

112

 

I/O

 

5VT

Default: PC11

Alternate: UART3_RX, SDIO_D3 Remap: USART2_RX, SPI2_MISO

 

PC12

 

113

 

I/O

 

5VT

Default: PC12

Alternate: UART4_TX, SDIO_CK

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

114

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2

Remap: CAN0_RX, OSCIN

 

PD1

 

115

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX, OSCOUT

 

PD2

 

116

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD

 

PD3

 

117

 

I/O

 

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS, TLI_G7, SPI1_SCK, I2S1_CK

 

PD4

 

118

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

119

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

VSS_10

120

 

 

Default: VSS_10

VDD_10

121

 

 

Default: VDD_10

 

PD6

 

122

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT

Remap: USART1_RX, TLI_B2, SPI2_MOSI, I2S2_SD

 

PD7

 

123

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

124

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2 Remap: USART5_RX

 

PG10

 

125

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2 Remap: TLI_G3, TLI_B2

 

PG11

 

126

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1 Remap: TLI_B3

PG12

127

I/O

5VT

Default: PG12

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: EXMC_NE3

Remap: USART5_RTS, TLI_B4, TLI_B1

 

PG13

 

128

 

I/O

 

5VT

Default: PG13

Alternate: EXMC_A24 Remap: USART5_CTS

 

PG14

 

129

 

I/O

 

5VT

Default: PG14 Alternate: EXMC_A25

Remap: USART5_TX

VSS_11

130

P

 

Default: VSS_10

VDD_11

131

P

 

Default: VDD_10

PG15

132

I/O

5VT

Default: PG15

Alternate: EXMC_SDNCAS, USART5_CTS

 

PB3

 

133

 

I/O

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK

 

PB4

 

134

 

I/O

 

5VT

Default: JNTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

 

PB5

 

 

135

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX,

EXMC_SDCKE1

 

 

PB6

 

 

136

 

 

I/O

 

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0

Remap: USART0_TX, CAN1_TX, EXMC_SDNE1, SPI0_IO3

 

PB7

 

137

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NL Remap: USART0_RX, SPI0_IO4

BOOT0

138

I

 

Default: BOOT0

 

PB8

 

139

 

I/O

 

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0, SDIO_D4 Remap: I2C0_SCL, CAN0_RX, TLI_B6

 

 

PB9

 

 

140

 

 

I/O

 

 

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0, SDIO_D5 Remap: I2C0_SDA, CAN0_TX, TLI_B7, SPI1_NSS,

I2S1_WS

PE0

141

I/O

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0, UART7_RX

 

PE1

 

142

 

I/O

 

5VT

Default: PE1

Alternate: EXMC_NBL1, UART7_TX

VSS_3

143

P

 

Default: VSS_3

VDD_3

144

P

 

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power.

(2)I/O Level: 5VT = 5 V tolerant.

ARM® Cortex®-M3 core

The Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M3 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 3072 Kbytes of flash memory, including code flash and data flash
Up to 256 Kbytes of SRAM

The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner flash at most, which includes code flash and data flash is available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. Up to 256 Kbytes of inner SRAM is composed of SRAM0, SRAM1, and SRAM2 that can be accessed at same time. Table 2-2 GD32F205xx memory map shows the memory map of the GD32F205xx series of devices, including flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB/APB2/APB1 domains is 120/120/60 MHz. See Figure 2-5. GD32F205xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6) and USB (PA9, PA10, PA11 and PA12). It also can be used to transfer and update the flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of flash memory is selected. It also supports to boot from bank 1 of flash memory by setting a bit in option bytes.

3.5.Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC engine with up to 2 MSPS conversion rate
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to three 12-bit 2 MSPS multi-channel ADC are integrated in the device. It is a total of up to 16 multiplexed external channels with 2 internal channels for temperature sensor and voltage reference measurement. The conversion range is between 2.6 V < VDDA < 3.6 V. An on-chip 16-bit hardware oversample scheme improves performances while off-loading the related computational burden from the MCU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally

connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

Digital to analog converter (DAC)

12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

14 channels DMA controller and each channel are configurable (7 for DMA0 and 7 for DMA1)
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S and SDIO

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 114 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 114 general purpose I/O pins (GPIO) in GD32F205xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH1 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull- up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with

digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)

The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a 16-bit general timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, known as TIMER1 ~ TIMER4, TIMER8 ~ TIMER13 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The general timer is based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. TIMER1 ~ TIMER4 and TIMER8/TIMER11 also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F205xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, it is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter.

The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC) and backup registers

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
84 bytes backup registers for data protection

The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
The backup registers are located in the backup domain that remains powered-on by VBAT even if VDD power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from standby mode or system reset do not affect these registers.
In addition, the backup registers can be used to implement the tamper detection, RTC calibration function and waveform detection.

Inter-integrated circuit (I2C)

Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking

for I2C data.


Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad wire configuration available in master mode (only in SPI0)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI0.

Universal    synchronous/asynchronous    receiver    transmitter (USART/UART)
Up to four USARTs and four UARTs with operating frequency up to 7.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6,
UART7) are used to transmit data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI1 and SPI2
Support either master or slave mode audio
Sampling frequencies from 8 KHz up to 192 KHz are supported.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F205xx contain an I2S-bus interface that can be operated with 16/32-bit resolution in master or slave mode, pin multiplexed with SPI1 and

SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.

Universal serial bus full-speed interface (USBFS)

One USB device/host full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and PC card, SDRAM with up to 32-bit data bus
Provide ECC calculating hardware module for NAND Flash memory block
Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits Column Address, 2-bits internal banks address
SDRAM Memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)
External memory controller (EXMC) is an abbreviation of external memory controller. It is divided into several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and PC card. The EXMC also can be

configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.
The EXMC of GD32F205xx in LQFP144 package also supports synchronous dynamic random access memory (SDRAM). It translates AHB transactions into the appropriate SDRAM protocol, and meanwhile, makes sure the access time requirements of the external SDRAM devices are satisfied.

Secure digital input and output card interface (SDIO)

Support SD2.0/SDIO2.0/MMC4.2 host interface

The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.

TFT LCD interface (TLI)

24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)
Supports up to SVGA (800x600) resolution

The TFT LCD interface provides a parallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display. Two separate layers are supported in TLI, as well as layer window and blending function.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F205Zx), LQFP100 (GD32F205Vx), LQFP64 (GD32F205Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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飞睿无线定位测距uwb标签UWB芯片厂商UWB定位公司实现无缝定位的领跑者

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18
2022-02

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

发布时间： : 2022-02--18
uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗，指纹门锁并不是什么新鲜事，我相信每个人都很熟悉。随着近年来智能家居的逐步普及，指纹门锁也进入了成千上万的家庭。今天的功耗雷达模块指纹门锁不仅消除了繁琐的钥匙，而且还提供了各种智能功能，uA级别智能门锁低功耗雷达模块用在智能门锁上，可以实现门锁的智能感应屏幕，使电池寿命延长3-5倍，如与其他智能家居连接，成为智能场景的开关。所以今天的指纹门锁更被称为智能门锁。 今天，让我们来谈谈功耗雷达模块智能门锁的安全性。希望能让更多想知道智能门锁的朋友认识下。 指纹识别是智能门锁的核心 指纹识别技术在我们的智能手机上随处可见。从以前的实体指纹识别到屏幕下的指纹识别，可以说指纹识别技术已经相当成熟。指纹识别可以说是整个uA级低功耗雷达模块智能门锁的核心。 目前主要有三种常见的指纹识别方法，即光学指纹识别、半导体指纹识别和超声指纹识别。 光学指纹识别 让我们先谈谈光学指纹识别的原理实际上是光的反射。我们都知道指纹本身是不均匀的。当光照射到我们的指纹上时，它会反射，光接收器可以通过接收反射的光来绘制我们的指纹。就像激光雷达测绘一样。 光学指纹识别通常出现在打卡机上，手机上的屏幕指纹识别技术也使用光学指纹识别。今天的光学指纹识别已经达到了非常快的识别速度。 然而，光学指纹识别有一个缺点，即硬件上的活体识别无法实现，容易被指模破解。通常，活体识别是通过软件算法进行的。如果算法处理不当，很容易翻车。 此外，光学指纹识别也容易受到液体的影响，湿手解锁的成功率也会下降。 超声指纹识别 超声指纹识别也被称为射频指纹识别，其原理与光学类型相似，但超声波使用声波反射，实际上是声纳的缩小版本。因为使用声波，不要担心水折射会降低识别率，所以超声指纹识别可以湿手解锁。然而，超声指纹识别在防破解方面与光学类型一样，不能实现硬件，可以被指模破解，活体识别仍然依赖于算法。 半导体指纹识别 半导体指纹识别主要采用电容、电场（即我们所说的电感）、温度和压力原理来实现指纹图像的收集。当用户将手指放在前面时，皮肤形成电容阵列的极板，电容阵列的背面是绝缘极板。由于不同区域指纹的脊柱与谷物之间的距离也不同，因此每个单元的电容量随之变化，从而获得指纹图像。半导体指纹识别具有价格低、体积小、识别率高的优点，因此大多数uA级低功耗雷达模块智能门锁都采用了这种方案。半导体指纹识别的另一个功能是活体识别。传统的硅胶指模无法破解。 当然，这并不意味着半导体可以百分识别活体。所谓的半导体指纹识别活体检测不使用指纹活体体征。本质上，它取决于皮肤的材料特性，这意味着虽然传统的硅胶指模无法破解。 一般来说，无论哪种指纹识别，都有可能被破解，只是说破解的水平。然而，今天的指纹识别，无论是硬件生活识别还是算法生活识别，都相对成熟，很难破解。毕竟，都可以通过支付级别的认证，大大保证安全。 目前，市场上大多数智能门锁仍将保留钥匙孔。除了指纹解锁外，用户还可以用传统钥匙开门。留下钥匙孔的主要目的是在指纹识别故障或智能门锁耗尽时仍有开门的方法。但由于有钥匙孔，它表明它可以通过技术手段解锁。 目前市场上的锁等级可分为A、B、C三个等级，这三个等级主要是通过防暴开锁和防技术开锁的程度来区分的。A级锁要求技术解锁时间不少于1分钟，B级锁要求不少于5分钟。即使是高级别的C级锁也只要求技术解锁时间不少于10分钟。 也就是说，现在市场上大多数门锁，无论是什么级别，在专业的解锁大师面前都糊，只不过是时间长短。 安全是重要的，是否安全增加了人们对uA级别低功耗雷达模块智能门锁安全的担忧。事实上，现在到处都是摄像头，强大的人脸识别，以及移动支付的出现，使家庭现金减少，所有这些都使得入室盗窃的成本急剧上升，近年来各省市的入室盗窃几乎呈悬崖状下降。 换句话说，无论锁有多安全，无论锁有多难打开，都可能比在门口安装摄像头更具威慑力。 因此，担心uA级别低功耗雷达模块智能门锁是否不安全可能意义不大。毕竟，家里的防盗锁可能不安全。我们应该更加关注门锁能给我们带来多少便利。 我们要考虑的是智能门锁的兼容性和通用性。毕竟，智能门锁近年来才流行起来。大多数人在后期将普通机械门锁升级为智能门锁。因此，智能门锁能否与原门兼容是非常重要的。如果不兼容，发现无法安装是一件非常麻烦的事情。 uA级别低功耗雷达模块智能门锁主要是为了避免带钥匙的麻烦。因此，智能门锁的便利性尤为重要。便利性主要体现在指纹的识别率上。手指受伤导致指纹磨损或老年人指纹较浅。智能门锁能否识别是非常重要的。 当然，如果指纹真的失效，是否有其他解锁方案，如密码解锁或NFC解锁。还需要注意密码解锁是否有虚假密码等防窥镜措施。 当然，智能门锁的耐久性也是一个需要特别注意的地方。uA级别低功耗雷达模块智能门锁主要依靠内部电池供电，这就要求智能门锁的耐久性尽可能好，否则经常充电或更换电池会非常麻烦。 智能门锁低功耗雷达模块：让门锁更加智能省电节约功耗 在当今信息化时代，智能门锁已经成为人们生活中不可或缺的一部分。对于门锁制造商来说，如何提高门锁的安全性、实用性和便利性，成为他们面对的重要课题。随着人们对门锁智能化的需求越来越高，门锁的能耗问题也成为了门锁制造商需要重视的问题。为此，越来越多的门锁制造商开始推出以低功耗为主题的系列产品。在这样的背景下，智能门锁低功耗雷达模块应运而生。 智能门锁低功耗雷达模块是一种新型技术，其采取雷达技术对门锁周围的物体进行探测，一旦发现门锁附近有人靠近，便会将门锁自动解锁，无需使用钥匙。同时，在保持智能控制的前提下，实现了门锁省电、节约功耗，延长门锁使用寿命。 在使用智能门锁低功耗雷达模块的门锁中，控制电路和自动解锁机制是关键的部件。控制电路采用先进的芯片技术，通过优秀的功耗控制以实现模块化管理。而自动解锁机制不仅可以通过微波信号控制实现门锁的无钥匙解锁，还能够在门锁未处理的情况下自动锁定，保障门锁的安全。 智能门锁低功耗雷达模块的主要特点是：低功耗、高灵敏度和高可靠性。该模块在进行人体检测时，可以远距离探测到距离为5-7米远处的人体信号，目标检测速度极快，而且对门锁周围的环境要求不高。同时，该模块采用了自适应自动补偿技术，能够根据不同环境的变化自动调整信号发射和接收参数，减小误检率。 在使用智能门锁低功耗雷达模块的门锁中，其功耗可以做到非常低，一组电池能够支持门锁持续使用几年左右。而且这样的智能门锁除了具有自动解锁的功能，还可与APP相互匹配，实现了远程操作的便捷性。 总的来说，智能门锁低功耗雷达模块的问世，解决了门锁安全性和省电节省方面的问题，是智能门锁材料不可或缺的一部分。作为门锁制造商，只有不断创新，利用这种新型技术，将会在行业中占据重要的地位。 除了上文所述的主要特点和优势，智能门锁低功耗雷达模块还具有以下几点： 1. 实时监测门锁周围环境变化，通过物体的距离体积和运动来确定是否有人靠近门锁，并控制门锁的开启或关闭，使得门锁更加智能化。 2. 可对门锁附件进行检测，如门挂、门应急照明灯以及紧急呼叫按钮等，并及时给出响应，确保门锁能够正常运作。这样，门锁在不受干扰的情况下，能够 保持安全通道。 3. 通过智能学习技术，能够自适应网站多种环境的变化，让智能门锁低功耗雷达模块更加准确和精细的控制门锁的开关，节约能耗并延长使用寿命。 4. 能够与其他智能电器相连，如智能家居系统、电视等，形成智能家居生态圈，更好地控制家庭访客进出，让生活更加方便。 综上所述，智能门锁低功耗雷达模块的出现，对提升门锁能耗管理和智能化有着重要作用。门锁制造商只有将这些新型技术运用到门锁产品中，才能更加贴合用户需求，满足消费市场的日益增长的智能化需求。
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14
2022-01

微波雷达传感器雷达感应浴室镜上的应用

发布时间： : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用，如今，家用电器的智能化已成为一种常态，越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入，今天就来说说这个话题。 什么是智能浴室镜？智慧型浴室镜，顾名思义，就是卫浴镜子智能化升级，入门级产品基本具备了彩灯和镜面触摸功能，更高档次的产品安装有微波雷达传感器智能感应，当感应到有人接近到一定距离即可开启亮灯或者亮屏操作，也可三色无极调，智能除雾，语音交互，日程安排备忘，甚至在镜子上看电视，听音乐，气象预报，问题查询，智能控制，健康管理等。 智能化雷达感应浴室镜与普通镜的区别，为什么要选TA？，就功能而言，普通浴镜价格用它没有什么压力！而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言，普通浴镜功能单一，而微波雷达传感器智能浴室镜功能创新：镜子灯光色温和亮度可以自由调节，镜面还可以湿手触控，智能除雾，既环保又健康！ 尽管智能浴镜比较新颖，但功能丰富，体验感更好，特别是入门级的智能浴镜，具有基础智能化功能，真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么？ ①确定智能浴室镜的安装位置，因为是安装时在墙壁上打孔，一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时，根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后，在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度，一般智能浴镜的标准安装高度约85cm(从地砖到镜子底)，具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍，可用酒精或30%清洁稀释液擦洗，平时可用干毛巾养护，注意多通风。
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05
2024-12

酒店吸顶雷达人体感应器的应用与优势

发布时间： : 2024-12--05
随着科技的飞速发展，智能化、人性化的服务理念在酒店行业中日益凸显其重要性。为了提升客人的居住体验，各大酒店纷纷引入了一系列先进的智能设备，其中，酒店吸顶雷达人体感应器以其独特的功能和高效的性能，成为现代酒店智能化改造中不可或缺的一部分。本文将详细介绍酒店吸顶雷达人体感应器的原理、功能、应用及优势，以期为酒店业的发展提供有益参考。 二、酒店吸顶雷达人体感应器概述 酒店吸顶雷达人体感应器是一种基于微波雷达技术的智能感应设备。它通过发射和接收微波信号，实时探测感应范围内的人体活动情况，并将探测结果转化为电信号输出，实现与酒店其他智能设备的联动控制。该感应器具有安装简便、探测准确、抗干扰能力强等优点，广泛应用于酒店客房、走廊、大堂等场所。 三、酒店吸顶雷达人体感应器的原理 酒店吸顶雷达人体感应器的工作原理主要基于多普勒效应。当感应器发射的微波信号遇到移动的人体时，信号频率会发生变化，感应器通过接收并分析这些变化后的信号，可以准确地判断出人体活动的位置、速度等信息。此外，该感应器还采用了先进的信号处理技术和算法，以提高探测的准确性和稳定性。 四、酒店吸顶雷达人体感应器的功能 人体探测：感应器能够实时监测感应范围内的人体活动情况，并将探测结果传输至酒店中央控制系统。 智能联动：感应器可以与酒店内的灯光、空调、窗帘等智能设备实现联动控制，根据人体活动情况自动调节设备的运行状态，提高居住舒适度。 节能环保：通过感应器的智能控制，酒店可以实现对灯光、空调等设备的精准管理，减少不必要的能源消耗，降低碳排放量，实现绿色环保。 数据分析：感应器还可以记录和分析人体活动数据，为酒店提供有价值的客户行为分析，帮助酒店优化服务流程，提升客户满意度。 五、酒店吸顶雷达人体感应器的应用 客房智能控制：在酒店客房内安装吸顶雷达人体感应器，可以实时监测客人的活动情况，自动调节灯光、空调等设备的运行状态。例如，当客人离开房间时，感应器可以自动关闭灯光和空调，节省能源；当客人回到房间时，感应器又可以自动开启灯光和空调，为客人营造舒适的居住环境。 走廊照明控制：在酒店走廊安装吸顶雷达人体感应器，可以实现走廊照明的智能控制。当感应器探测到有人经过时，可以自动开启走廊灯光；当无人经过时，则自动关闭灯光，既保证了走廊的照明需求，又避免了不必要的能源浪费。 大堂人流监测：在酒店大堂安装吸顶雷达人体感应器，可以实时监测大堂内的人流情况，为酒店提供有价值的数据支持。通过分析这些数据，酒店可以了解大堂的客流高峰时段、客户停留时间等信息，为优化服务流程、提升客户满意度提供依据。 安全防范：除了基本的感应功能外，酒店吸顶雷达人体感应器还可以与酒店的安全防范系统相结合，实现更别的安全保障。例如，当感应器探测到异常的人体活动（如长时间静止不动或快速移动）时，可以自动触发报警系统，提醒酒店工作人员及时处理，确保客人的安全。 六、酒店吸顶雷达人体感应器的优势 高效节能：通过智能控制灯光、空调等设备，酒店吸顶雷达人体感应器能够显著降低能源消耗，为酒店带来经济效益的同时，也为环保事业做出了贡献。 提升客户体验：感应器能够实时响应客人的需求，自动调节设备的运行状态，为客人营造更加舒适、便捷的居住环境，提升客户满意度。 数据支持：感应器可以记录和分析人体活动数据，为酒店提供有价值的客户行为分析，帮助酒店优化服务流程、提升服务质量。 易于安装和维护：酒店吸顶雷达人体感应器采用模块化设计，安装简便快捷；同时，其稳定性和耐用性也经过了严格测试，可大大降低酒店的维护成本。 七、结语 酒店吸顶雷达人体感应器作为一种先进的智能感应设备，在提升酒店智能化水平、优化客户体验、降低能源消耗等方面发挥着重要作用。随着科技的不断进步和酒店业的不断发展，相信酒店吸顶雷达人体感应器将在未来发挥更加重要的作用。同时，我们也期待更多优秀的智能设备和技术能够不断涌现，为酒店业的发展注入新的活力。
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04
2024-12

酒店雷达人体呼吸传感器原理及应用探究

发布时间： : 2024-12--04
随着科技的飞速发展，智能化已成为现代生活的重要特征。在酒店行业中，为了提升客人的入住体验，各种智能化设备和技术层出不穷。其中，雷达人体呼吸传感器作为一种新型智能传感设备，以其独特的原理和优势，逐渐受到酒店业的青睐。本文将对酒店雷达人体呼吸传感器的原理进行详细介绍，并探讨其在酒店中的应用及其带来的积影响。 二、酒店雷达人体呼吸传感器原理 雷达人体呼吸传感器，作为一种基于雷达技术的智能传感设备，通过发射和接收雷达波来探测和追踪人体的动作和位置。其原理主要是利用雷达波在空气中传播时遇到障碍物会反射回来的特性，通过分析反射回来的雷达波信号，判断人体在特定区域内的存在和活动情况。 在酒店雷达人体呼吸传感器中，通常采用的是毫米波雷达技术。毫米波雷达技术具有波长短、穿透能力强、抗干扰性好等优点，能够在复杂的环境中准确地探测到人体的存在和活动情况。同时，毫米波雷达技术还能够通过处理反射回来的雷达波信号，提取出人体的呼吸和心跳等生理信息，从而实现对人体状态的实时监测。 具体来说，酒店雷达人体呼吸传感器的工作原理可以分为以下几个步骤： 雷达波发射：传感器通过天线发射毫米波雷达波，这些雷达波在空气中传播并遇到障碍物时会被反射回来。 信号接收与处理：传感器通过天线接收反射回来的雷达波信号，并对这些信号进行放大、滤波和数字化处理。处理后的信号被送入微处理器进行进一步的分析和处理。 人体检测与识别：微处理器通过对处理后的信号进行算法分析和比对，判断是否存在人体目标。如果存在人体目标，则进一步提取出人体的呼吸等生理信息。 数据输出与应用：传感器将检测到的人体信息通过有线或无线方式传输给酒店管理系统或其他智能设备，实现自动控制、安全保障等功能。 三、酒店雷达人体呼吸传感器的应用 酒店雷达人体呼吸传感器作为一种新型智能传感设备，在酒店中具有广泛的应用前景。以下是几个典型的应用场景： 入住体验提升：在酒店客房中安装雷达人体呼吸传感器，可以实时监测客人的活动情况，并根据客人的需求自动调节房间内的温度、湿度、照明等环境参数，为客人提供更加舒适、个性化的入住体验。 节能环保：通过雷达人体呼吸传感器实时监测客人的活动情况，可以智能控制房间内的灯光、空调等设备的开关和运行状态，避免不必要的能源浪费，实现节能环保的目标。 安全保障：雷达人体呼吸传感器可以与酒店的安全监测系统集成，实时监测客房内的安全状况。当传感器检测到异常情况时，可以自动触发警报系统并通知酒店管理人员进行处理，确保客人的安全。 数据分析与优化：通过对雷达人体呼吸传感器收集的数据进行分析和处理，酒店可以了解客人的生活习惯和偏好等信息，为酒店服务和管理提供数据支持。同时，这些数据还可以用于优化酒店的服务流程和管理策略，提高酒店的运营效率和客户满意度。 四、酒店雷达人体呼吸传感器的优势 酒店雷达人体呼吸传感器相比传统的人体感应设备具有以下优势： 高精度探测：雷达人体呼吸传感器采用毫米波雷达技术，能够高精度地探测到人体的存在和活动情况，避免了传统设备可能出现的误报和漏报问题。 宽范围探测：雷达人体呼吸传感器的探测范围广泛，可以覆盖整个客房区域甚至公共区域，为酒店提供了更加全面、准确的探测能力。 抗干扰能力强：毫米波雷达技术具有抗干扰性好的特点，能够在复杂的环境中稳定工作，确保探测结果的准确性和可靠性。 智能化程度高：雷达人体呼吸传感器可以与酒店管理系统和其他智能设备无缝对接，实现自动化控制、数据分析等功能，提高了酒店的智能化水平。 五、结论 酒店雷达人体呼吸传感器作为一种新型智能传感设备，在提升酒店入住体验、节能环保、安全保障等方面具有显著的优势。随着科技的不断发展和进步，相信雷达人体呼吸传感器将在酒店行业中发挥更加重要的作用，为客人带来更加智能、舒适、安全的入住体验。同时，我们也期待更多的技术创新和应用场景的探索，推动酒店业的持续发展和进步。
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03
2024-12

智能家居人体传感器呼吸静止不动探测雷达感应器

发布时间： : 2024-12--03
在智能家居的浪潮中，人体传感器凭借其独特的功能性和智能化，逐渐成为了家居安全、舒适与便捷的重要一环。其中，呼吸静止不动雷达感应器作为一种新兴技术，以其高精度、非接触式监测的特点，受到了越来越多消费者的青睐。本文将深入探讨人体传感器呼吸静止不动探测雷达感应器在智能家居领域的应用，以及它如何为我们的家居生活带来创新性的变化。 一、人体传感器呼吸静止不动探测雷达感应器的工作原理 人体传感器呼吸静止不动探测雷达感应器是一种基于微波雷达技术的传感器，它通过发射微波信号并接收反射信号，来探测人体在静止或呼吸状态下的微小动作。这种技术不仅可以检测到人体的移动，还能够准确地捕捉到人体的呼吸，甚至是在人体完全静止不动的情况下。 与传统的红外传感器相比，呼吸静止不动探测雷达感应器具有更高的灵敏度和更广的探测范围。它不受光线、温度等环境因素的影响，能够在各种复杂环境下稳定工作。此外，由于雷达信号对人体无害，因此这种传感器在智能家居领域具有高的应用前景。 二、呼吸静止不动雷达感应器在智能家居中的应用 睡眠监测与改善 呼吸静止不动探测雷达感应器可以实时监测用户的睡眠状态，包括呼吸频率、睡眠时长、睡眠深度等关键指标。通过将这些数据上传至智能家居系统，用户可以随时随地了解自己的睡眠质量，并根据系统提供的建议进行改善。同时，智能家居系统还可以根据用户的睡眠状态，自动调节卧室的温度、湿度、光线等环境参数，为用户创造一个更加舒适的睡眠环境。 安全防护与报警 人体传感器呼吸静止不动探测雷达感应器还可以用于家居安全防护。当用户在卧室或卫生间等私密空间内长时间静止不动时，传感器会发出警报，提醒用户注意安全。此外，它还可以与智能家居系统联动，实现自动报警、紧急呼叫等功能，确保用户在遭遇突发情况时能够得到及时救助。 节能环保与智能化控制 通过呼吸静止不动探测雷达感应器，智能家居系统可以准确地识别房间内的实际使用情况。当房间内无人时，系统可以自动关闭灯光、空调等电器设备，从而达到节能环保的目的。同时，这种技术还可以实现更加智能化的控制策略，如根据用户的生活习惯和喜好，自动调节家居设备的运行模式和参数。 三、人体传感器呼吸静止不动探测雷达感应器的技术优势 高精度监测 呼吸静止不动探测雷达感应器采用先进的微波雷达技术，具有高的监测精度。它可以准确地捕捉到人体的呼吸频率和微小动作，为用户提供更加准确的监测数据。 非接触式监测 这种传感器无需与用户直接接触，即可实现对人体的实时监测。这不仅提高了用户的舒适度，还避免了因接触式监测可能带来的卫生问题。 抗干扰能力强 呼吸静止不动探测雷达感应器不受光线、温度等环境因素的影响，能够在各种复杂环境下稳定工作。这使得它在智能家居领域具有更广泛的应用前景。 安全性高 雷达信号对人体无害，因此呼吸静止不动探测雷达感应器在使用过程中具有较高的安全性。用户可以放心地使用这种传感器来监测自己的健康状况和家居安全。 四、未来展望 随着智能家居技术的不断发展，人体传感器呼吸静止不动探测雷达感应器将在更多领域得到应用。未来，我们可以期待这种传感器在医疗健康、养老护理、安全防护等方面发挥更大的作用。同时，随着技术的不断进步和成本的降低，这种传感器将更加普及化、平民化，为更多家庭带来智能化、便捷化的生活体验。 总之，人体传感器呼吸静止不动探测雷达感应器作为智能家居领域的一种新兴技术，以其高精度、非接触式监测的特点，为我们的家居生活带来了创新性的变化。随着技术的不断发展和普及化应用，我们有理由相信，未来的智能家居将更加智能化、便捷化、舒适化。
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