兆易创新GD32E230G8U6-GD32 ARM Cortex-M23 Microcontroller
兆易创新GD32E230G8U6-GD32 ARM Cortex-M23 Microcontroller
GigaDevice Semiconductor Inc.
GD32E230xx
ARM® Cortex®-M23 32-bit MCU
Datasheet
General description
The GD32E230xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M23 core. The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor delivers high energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier and a 17-cycle divider.
The GD32E230xx device incorporates the ARM® Cortex®-M23 32-bit processor core operating at up to 72 MHz frequency with Flash accesses 0~2 wait states to obtain maximum efficiency. It provides up to 64 KB embedded Flash memory and up to 8 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC and one comparator, up to five general 16-bit timers, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, and an I2S.
The device operates from a 1.8 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32E230xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.
Device information
Table 2-1. GD32E230xx devices features and peripheral list
Part Number |
GD32E230xx |
|||||||||
|
K4U6 |
K6U6 |
K8U6 |
K4T6 |
K6T6 |
K8T6 |
C4T6 |
C6T6 |
C8T6 |
|
FLASH (KB) |
16 |
32 |
64 |
16 |
32 |
64 |
16 |
32 |
64 |
|
SRAM (KB) |
4 |
6 |
8 |
4 |
4 |
8 |
4 |
6 |
8 |
|
Timers |
General timer(16-bit) |
4 (2,13,15,16) |
4 (2,13,15,16) |
5 (2,13-16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
5 (2,13-16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
5 (2,13-16) |
|
Advanced timer(16-bit) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
|
SysTick |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
Basic timer(16-bit) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
|
Watchdog |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
RTC |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Connectivity |
USART |
1 (0) |
2 (0-1) |
2 (0-1) |
1 (0) |
2 (0-1) |
2 (0-1) |
1 (0) |
2 (0-1) |
2 (0-1) |
|
I2C |
1 (0) |
1 (0) |
2 (0-1) |
1 (0) |
1 (0) |
2 (0-1) |
1 (0) |
1 (0) |
2 (0-1) |
|
SPI/I2S |
1/1 (0)/(0) |
1/1 (0)/(0) |
2/1 (0-1)/(0) |
1/1 (0)/(0) |
1/1 (0)/(0) |
2/1 (0-1)/(0) |
1/1 (0)/(0) |
1/1 (0)/(0) |
2/1 (0-1)/(0) |
GPIO |
27 |
27 |
27 |
25 |
25 |
25 |
39 |
39 |
39 |
|
CMP |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
EXTI |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
|
ADC |
Units |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
Channels (External) |
10 |
10 |
10 |
10 |
10 |
10 |
10 |
10 |
10 |
|
Channels (Internal) |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
Package |
QFN32 |
LQFP32 |
LQFP48 |
Part Number |
GD32E230xx |
|||||||||
|
F4V6 |
F6V6 |
F8V6 |
F4P6 |
F6P6 |
F8P6 |
G4U6 |
G6U6 |
G8U6 |
|
FLASH (KB) |
16 |
32 |
64 |
16 |
32 |
64 |
16 |
32 |
64 |
|
SRAM (KB) |
4 |
6 |
8 |
4 |
6 |
8 |
4 |
6 |
8 |
|
Timers |
General timer(16-bit) |
4 (2,13,15,16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
4 (2,13,15,16) |
5 (2,13-16) |
|
Advanced timer(16-bit) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
1 (0) |
|
SysTick |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
Basic timer(16-bit) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
1 (5) |
|
Watchdog |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
|
RTC |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Connectivity |
USART |
1 (0) |
2 (0-1) |
2 (0-1) |
1 (0) |
2 (0-1) |
2 (0-1) |
1 (0) |
2 (0-1) |
2 (0-1) |
|
I2C |
1 (0) |
1 (0) |
2 (0-1) |
1 (0) |
1 (0) |
2 (0-1) |
1 (0) |
1 (0) |
2 (0-1) |
|
SPI/I2S |
1/1 (0)/(0) |
1/1 (0)/(0) |
2/1 (0-1)/(0) |
1/1 (0)/(0) |
1/1 (0)/(0) |
2/1 (0-1)/(0) |
1/1 (0)/(0) |
1/1 (0)/(0) |
2/1 (0-1)/(0) |
GPIO |
15 |
15 |
15 |
15 |
15 |
15 |
23 |
23 |
23 |
|
CMP |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
EXTI |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
16 |
|
ADC |
Units |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
Channels (External) |
9 |
9 |
9 |
9 |
9 |
9 |
10 |
10 |
10 |
|
Channels (Internal) |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
Package |
LGA20 |
TSSOP20 |
QFN28 |
Memory map
Table 2-3. GD32E230xx memory map
Pre-defined Regions |
Bus |
ADDRESS |
Peripherals |
|
|
0xE000 0000 - 0xE00F FFFF |
Cortex M23 internal peripherals |
External Device |
|
0xA000 0000 - 0xDFFF FFFF |
Reserved |
External RAM |
|
0x60000000 - 0x9FFFFFFF |
Reserved |
Peripherals |
AHB1 |
0x5004 0000 - 0x5FFF FFFF |
Reserved |
|
|
0x5000 0000 - 0x5003 FFFF |
Reserved |
|
AHB2 |
0x4800 1800 - 0x4FFF FFFF |
Reserved |
|
|
0x4800 1400 - 0x4800 17FF |
GPIOF |
|
|
0x4800 1000 - 0x4800 13FF |
Reserved |
|
|
0x4800 0C00 - 0x4800 0FFF |
Reserved |
|
|
0x4800 0800 - 0x4800 0BFF |
GPIOC |
|
|
0x4800 0400 - 0x4800 07FF |
GPIOB |
|
|
0x4800 0000 - 0x4800 03FF |
GPIOA |
|
AHB1 |
0x4002 4400 - 0x47FF FFFF |
Reserved |
|
|
0x4002 4000 - 0x4002 43FF |
Reserved |
|
|
0x4002 3400 - 0x4002 3FFF |
Reserved |
|
|
0x4002 3000 - 0x4002 33FF |
CRC |
|
|
0x4002 2400 - 0x4002 2FFF |
Reserved |
|
|
0x4002 2000 - 0x4002 23FF |
FMC |
|
|
0x4002 1400 - 0x4002 1FFF |
Reserved |
|
|
0x4002 1000 - 0x4002 13FF |
RCU |
|
|
0x4002 0400 - 0x4002 0FFF |
Reserved |
|
|
0x4002 0000 - 0x4002 03FF |
DMA |
|
APB2 |
0x4001 8000 - 0x4001 FFFF |
Reserved |
|
|
0x4001 5C00 - 0x4001 7FFF |
Reserved |
|
|
0x4001 5800 - 0x4001 5BFF |
DBG |
|
|
0x4001 4C00 - 0x4001 57FF |
Reserved |
|
|
0x4001 4800 - 0x4001 4BFF |
TIMER16 |
|
|
0x4001 4400 - 0x4001 47FF |
TIMER15 |
|
|
0x4001 4000 - 0x4001 43FF |
TIMER14 |
|
|
0x4001 3C00 - 0x4001 3FFF |
Reserved |
|
|
0x4001 3800 - 0x4001 3BFF |
USART0 |
|
|
0x4001 3400 - 0x4001 37FF |
Reserved |
|
|
0x4001 3000 - 0x4001 33FF |
SPI0/I2S0 |
|
|
0x4001 2C00 - 0x4001 2FFF |
TIMER0 |
|
|
0x4001 2800 - 0x4001 2BFF |
Reserved |
|
|
0x4001 2400 - 0x4001 27FF |
ADC |
|
|
0x4001 0800 - 0x4001 23FF |
Reserved |
Pre-defined Regions |
Bus |
ADDRESS |
Peripherals |
|
|
0x4001 0400 - 0x4001 07FF |
EXTI |
|
|
0x4001 0000 - 0x4001 03FF |
SYSCFG + CMP |
|
APB1 |
0x4000 CC00 - 0x4000 FFFF |
Reserved |
|
|
0x4000 C800 - 0x4000 CBFF |
Reserved |
|
|
0x4000 C400 - 0x4000 C7FF |
Reserved |
|
|
0x4000 C000 - 0x4000 C3FF |
Reserved |
|
|
0x4000 8000 - 0x4000 BFFF |
Reserved |
|
|
0x4000 7C00 - 0x4000 7FFF |
Reserved |
|
|
0x4000 7800 - 0x4000 7BFF |
Reserved |
|
|
0x4000 7400 - 0x4000 77FF |
Reserved |
|
|
0x4000 7000 - 0x4000 73FF |
PMU |
|
|
0x4000 6400 - 0x4000 6FFF |
Reserved |
|
|
0x4000 6000 - 0x4000 63FF |
Reserved |
|
|
0x4000 5C00 - 0x4000 5FFF |
Reserved |
|
|
0x4000 5800 - 0x4000 5BFF |
I2C1 |
|
|
0x4000 5400 - 0x4000 57FF |
I2C0 |
|
|
0x4000 4800 - 0x4000 53FF |
Reserved |
|
|
0x4000 4400 - 0x4000 47FF |
USART1 |
|
|
0x4000 4000 - 0x4000 43FF |
Reserved |
|
|
0x4000 3C00 - 0x4000 3FFF |
Reserved |
|
|
0x4000 3800 - 0x4000 3BFF |
SPI1 |
|
|
0x4000 3400 - 0x4000 37FF |
Reserved |
|
|
0x4000 3000 - 0x4000 33FF |
FWDGT |
|
|
0x4000 2C00 - 0x4000 2FFF |
WWDGT |
|
|
0x4000 2800 - 0x4000 2BFF |
RTC |
|
|
0x4000 2400 - 0x4000 27FF |
Reserved |
|
|
0x4000 2000 - 0x4000 23FF |
TIMER13 |
|
|
0x4000 1400 - 0x4000 1FFF |
Reserved |
|
|
0x4000 1000 - 0x4000 13FF |
TIMER5 |
|
|
0x4000 0800 - 0x4000 0FFF |
Reserved |
|
|
0x4000 0400 - 0x4000 07FF |
TIMER2 |
|
|
0x4000 0000 - 0x4000 03FF |
Reserved |
SRAM |
|
0x2000 2000 - 0x3FFF FFFF |
Reserved |
|
|
0x2000 0000 - 0x2000 1FFF |
SRAM |
Code |
|
0x1FFF F810 - 0x1FFF FFFF |
Reserved |
|
|
0x1FFF F800 - 0x1FFF F80F |
Option bytes |
|
|
0x1FFF EC00 - 0x1FFF F7FF |
System memory |
|
|
0x0801 0000 - 0x1FFF EBFF |
Reserved |
|
|
0x0800 0000 - 0x0800 FFFF |
Main Flash memory |
|
|
0x0001 0000 - 0x07FF FFFF |
Reserved |
GD32E230Cx LQFP48 pin definitions
Table 2-4. GD32E230Cx LQFP48 pin definitions
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
VDD |
1 |
P |
|
Default: VDD |
PC13- TAMPER- RTC |
2 |
I/O |
|
Default: PC13 Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1 |
PC14- OSC32IN |
3 |
I/O |
|
Default: PC14 Additional: OSC32IN |
PC15- OSC32OUT |
4 |
I/O |
|
Default: PC15 Additional: OSC32OUT |
PF0-OSCIN |
5 |
I/O |
5VT |
Default: PF0 Alternate: I2C0_SDA Additional: OSCIN |
PF1- OSCOUT |
6 |
I/O |
5VT |
Default: PF1 Alternate: I2C0_SCL Additional: OSCOUT |
NRST |
7 |
I/O |
|
Default: NRST |
VSSA |
8 |
P |
|
Default: VSSA |
VDDA |
9 |
P |
|
Default: VDDA |
PA0-WKUP |
10 |
I/O |
|
Default: PA0 Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 |
PA1 |
11 |
I/O |
|
Default: PA1 Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) Additional: ADC_IN1, CMP_IP |
PA2 |
12 |
I/O |
|
Default: PA2 Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 |
PA3 |
13 |
I/O |
|
Default: PA3 Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) Additional: ADC_IN3 |
PA4 |
14 |
I/O |
|
Default: PA4 Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
Default: PA5 |
PA5 |
15 |
I/O |
|
Alternate: SPI0_SCK, I2S0_CK |
|
|
|
|
Additional: ADC_IN5, CMP_IM5 |
|
|
|
|
Default: PA6 |
|
|
|
|
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, |
PA6 |
16 |
I/O |
|
TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, |
|
|
|
|
CMP_OUT |
|
|
|
|
Additional: ADC_IN6 |
|
|
|
|
Default: PA7 |
|
|
|
|
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, |
PA7 |
17 |
I/O |
|
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, |
|
|
|
|
EVENTOUT |
|
|
|
|
Additional: ADC_IN7 |
|
|
|
|
Default: PB0 |
PB0 |
18 |
I/O |
|
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT |
|
|
|
|
Additional: ADC_IN8 |
|
|
|
|
Default: PB1 |
PB1 |
19 |
I/O |
|
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5) |
|
|
|
|
Additional: ADC_IN9 |
PB2 |
20 |
I/O |
5VT |
Default: PB2 Alternate: TIMER2_ETI |
|
|
|
|
Default: PB10 |
PB10 |
21 |
I/O |
5VT |
Alternate: I2C0_SCL(3),I2C1_SCL(5), SPI1_IO2(5), |
|
|
|
|
SPI1_SCK(5) |
|
|
|
|
Default: PB11 |
PB11 |
22 |
I/O |
5VT |
Alternate: I2C0_SDA(3),I2C1_SDA(5), EVENTOUT, |
|
|
|
|
SPI1_IO3(5) |
VSS |
23 |
P |
|
Default: VSS |
VDD |
24 |
P |
|
Default: VDD |
|
|
|
|
Default: PB12 |
PB12 |
25 |
I/O |
5VT |
Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BRKIN, |
|
|
|
|
I2C1_SMBA(5), EVENTOUT |
|
|
|
|
Default: PB13 |
PB13 |
26 |
I/O |
5VT |
Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON, |
|
|
|
|
I2C1_TXFRAME(5), I2C1_SCL(5) |
|
|
|
|
Default: PB14 |
PB14 |
27 |
I/O |
5VT |
Alternate: SPI0_MISO(3), SPI1_MISO(5), |
|
|
|
|
TIMER0_CH1_ON, TIMER14_CH0(5), I2C1_SDA(5) |
|
|
|
|
Default: PB15 |
|
|
|
|
Alternate: SPI0_MOSI(3), SPI1_MOSI(5), |
PB15 |
28 |
I/O |
5VT |
TIMER0_CH2_ON, TIMER14_CH0_ON(5), |
|
|
|
|
TIMER14_CH1(5) |
|
|
|
|
Additional: RTC_REFIN, WKUP6 |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
PA8 |
29 |
I/O |
5VT |
Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT |
PA9 |
30 |
I/O |
5VT |
Default: PA9 Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT |
PA10 |
31 |
I/O |
5VT |
Default: PA10 Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA |
PA11 |
32 |
I/O |
5VT |
Default: PA11 Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5) |
PA12 |
33 |
I/O |
5VT |
Default: PA12 Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5) |
PA13 |
34 |
I/O |
5VT |
Default: PA13/SWDIO Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) |
PF6 |
35 |
I/O |
5VT |
Default: PF6 Alternate: I2C0_SCL(3), I2C1_SCL(5) |
PF7 |
36 |
I/O |
5VT |
Default: PF7 Alternate: I2C0_SDA(3), I2C1_SDA(5) |
PA14 |
37 |
I/O |
5VT |
Default: PA14/SWCLK Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) |
PA15 |
38 |
I/O |
5VT |
Default: PA15 Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT |
PB3 |
39 |
I/O |
5VT |
Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT |
PB4 |
40 |
I/O |
5VT |
Default: PB4 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN |
PB5 |
41 |
I/O |
5VT |
Default: PB5 Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 |
PB6 |
42 |
I/O |
5VT |
Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON |
PB7 |
43 |
I/O |
5VT |
Default: PB7 Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON |
BOOT0 |
44 |
I |
|
Default: BOOT0 |
PB8 |
45 |
I/O |
5VT |
Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 |
PB9 |
46 |
I/O |
5VT |
Default: PB9 Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0, |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
EVENTOUT, I2S0_MCK, SPI1_NSS(5) |
VSS |
47 |
P |
|
Default: VSS |
VDD |
48 |
P |
|
Default: VDD |
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32E230C4 devices only.
(4)Functions are available on GD32E230C8/6 devices.
(5)Functions are available on GD32E230C8 devices only.
GD32E230Kx LQFP32 pin definitions
Table 2-5. GD32E230Kx LQFP32 pin definitions
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
VDD |
1 |
P |
|
Default: VDD |
PF0-OSCIN |
2 |
I/O |
5VT |
Default: PF0 Alternate: I2C0_SDA Additional: OSCIN |
PF1- OSCOUT |
3 |
I/O |
5VT |
Default: PF1 Alternate: I2C0_SCL Additional: OSCOUT |
NRST |
4 |
I/O |
|
Default: NRST |
VDDA |
5 |
P |
|
Default: VDDA |
PA0-WKUP |
6 |
I/O |
|
Default: PA0 Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 |
PA1 |
7 |
I/O |
|
Default: PA1 Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) Additional: ADC_IN1, CMP_IP |
PA2 |
8 |
I/O |
|
Default: PA2 Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 |
PA3 |
9 |
I/O |
|
Default: PA3 Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) Additional: ADC_IN3 |
PA4 |
10 |
I/O |
|
Default: PA4 Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
Additional: ADC_IN4, CMP_IM4 |
|
|
|
|
Default: PA5 |
PA5 |
11 |
I/O |
|
Alternate: SPI0_SCK, I2S0_CK |
|
|
|
|
Additional: ADC_IN5, CMP_IM5 |
|
|
|
|
Default: PA6 |
|
|
|
|
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, |
PA6 |
12 |
I/O |
|
TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, |
|
|
|
|
CMP_OUT |
|
|
|
|
Additional: ADC_IN6 |
|
|
|
|
Default: PA7 |
|
|
|
|
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, |
PA7 |
13 |
I/O |
|
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, |
|
|
|
|
EVENTOUT |
|
|
|
|
Additional: ADC_IN7 |
|
|
|
|
Default: PB0 |
PB0 |
14 |
I/O |
|
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT |
|
|
|
|
Additional: ADC_IN8 |
|
|
|
|
Default: PB1 |
PB1 |
15 |
I/O |
|
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5) |
|
|
|
|
Additional: ADC_IN9 |
VSS |
16 |
P |
|
Default: VSS |
VDD |
17 |
P |
|
Default: VDD |
|
|
|
|
Default: PA8 |
PA8 |
18 |
I/O |
5VT |
Alternate: USART0_CK, TIMER0_CH0, CK_OUT, |
|
|
|
|
USART1_TX(4), EVENTOUT |
|
|
|
|
Default: PA9 |
PA9 |
19 |
I/O |
5VT |
Alternate: USART0_TX, TIMER0_CH1, |
|
|
|
|
TIMER14_BRKIN(5), I2C0_SCL, CK_OUT |
|
|
|
|
Default: PA10 |
PA10 |
20 |
I/O |
5VT |
Alternate: USART0_RX, TIMER0_CH2, |
|
|
|
|
TIMER16_BRKIN, I2C0_SDA |
|
|
|
|
Default: PA11 |
PA11 |
21 |
I/O |
5VT |
Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, |
|
|
|
|
EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5) |
|
|
|
|
Default: PA12 |
PA12 |
22 |
I/O |
5VT |
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, |
|
|
|
|
SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5) |
PA13 |
23 |
I/O |
5VT |
Default: PA13/SWDIO Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) |
|
|
|
|
Default: PA14/SWCLK |
PA14 |
24 |
I/O |
5VT |
Alternate: USART0_TX(3), USART1_TX(4), SWCLK, |
|
|
|
|
SPI1_MOSI(5) |
PA15 |
25 |
I/O |
5VT |
Default: PA15 Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
USART1_RX(4), SPI1_NSS(5), EVENTOUT |
PB3 |
26 |
I/O |
5VT |
Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT |
PB4 |
27 |
I/O |
5VT |
Default: PB4 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN |
PB5 |
28 |
I/O |
5VT |
Default: PB5 Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 |
PB6 |
29 |
I/O |
5VT |
Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON |
PB7 |
30 |
I/O |
5VT |
Default: PB7 Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON |
BOOT0 |
31 |
I |
|
Default: BOOT0 |
VSS |
32 |
P |
|
Default: VSS |
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32E230K4 devices only.
(4)Functions are available on GD32E230K8/6 devices.
(5)Functions are available on GD32E230K8 devices only.
GD32E230Kx QFN32 pin definitions
Table 2-6. GD32E230Kx QFN32 pin definitions
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
VDD |
1 |
P |
|
Default: VDD |
PF0-OSCIN |
2 |
I/O |
5VT |
Default: PF0 Alternate: I2C0_SDA Additional: OSCIN |
PF1- OSCOUT |
3 |
I/O |
5VT |
Default: PF1 Alternate: I2C0_SCL Additional: OSCOUT |
NRST |
4 |
I/O |
|
Default: NRST |
VDDA |
5 |
P |
|
Default: VDDA |
PA0-WKUP |
6 |
I/O |
|
Default: PA0 Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 |
PA1 |
7 |
I/O |
|
Default: PA1 Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
Additional: ADC_IN1, CMP_IP |
PA2 |
8 |
I/O |
|
Default: PA2 Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 |
PA3 |
9 |
I/O |
|
Default: PA3 Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) Additional: ADC_IN3 |
PA4 |
10 |
I/O |
|
Default: PA4 Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 |
PA5 |
11 |
I/O |
|
Default: PA5 Alternate: SPI0_SCK, I2S0_CK Additional: ADC_IN5, CMP_IM5 |
PA6 |
12 |
I/O |
|
Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, CMP_OUT Additional: ADC_IN6 |
PA7 |
13 |
I/O |
|
Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 |
PB0 |
14 |
I/O |
|
Default: PB0 Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT Additional: ADC_IN8 |
PB1 |
15 |
I/O |
|
Default: PB1 Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 |
PB2 |
16 |
I/O |
5VT |
Default: PB2 Alternate: TIMER2_ETI |
VDD |
17 |
P |
|
Default: VDD |
PA8 |
18 |
I/O |
5VT |
Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT |
PA9 |
19 |
I/O |
5VT |
Default: PA9 Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT |
PA10 |
20 |
I/O |
5VT |
Default: PA10 Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
PA11 |
21 |
I/O |
5VT |
Default: PA11 Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5) |
PA12 |
22 |
I/O |
5VT |
Default: PA12 Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5) |
PA13 |
23 |
I/O |
5VT |
Default: PA13/SWDIO Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) |
PA14 |
24 |
I/O |
5VT |
Default: PA14/SWCLK Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) |
PA15 |
25 |
I/O |
5VT |
Default: PA15 Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT |
PB3 |
26 |
I/O |
5VT |
Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT |
PB4 |
27 |
I/O |
5VT |
Default: PB4 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN |
PB5 |
28 |
I/O |
5VT |
Default: PB5 Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 |
PB6 |
29 |
I/O |
5VT |
Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON |
PB7 |
30 |
I/O |
5VT |
Default: PB7 Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON |
BOOT0 |
31 |
I |
|
Default: BOOT0 |
PB8 |
32 |
I/O |
5VT |
Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 |
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32E230K4 devices only.
(4)Functions are available on GD32E230K8/6 devices.
(5)Functions are available on GD32E230K8 devices only.
GD32E230Gx QFN28 pin definitions
Table 2-7. GD32E230Gx QFN28 pin definitions
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
BOOT0 |
1 |
I |
|
Default: BOOT0 |
PF0-OSCIN |
2 |
I/O |
5VT |
Default: PF0 |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
Alternate: I2C0_SDA |
|
|
|
|
Additional: OSCIN |
PF1- OSCOUT |
3 |
I/O |
5VT |
Default: PF1 Alternate: I2C0_SCL Additional: OSCOUT |
NRST |
4 |
I/O |
|
Default: NRST |
VDDA |
5 |
P |
|
Default: VDDA |
|
|
|
|
Default: PA0 |
PA0-WKUP |
6 |
I/O |
|
Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) |
|
|
|
|
Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 |
|
|
|
|
Default: PA1 |
PA1 |
7 |
I/O |
|
Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) |
|
|
|
|
Additional: ADC_IN1, CMP_IP |
|
|
|
|
Default: PA2 |
PA2 |
8 |
I/O |
|
Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) |
|
|
|
|
Additional: ADC_IN2, CMP_IM7 |
|
|
|
|
Default: PA3 |
PA3 |
9 |
I/O |
|
Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) |
|
|
|
|
Additional: ADC_IN3 |
|
|
|
|
Default: PA4 |
PA4 |
10 |
I/O |
|
Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) |
|
|
|
|
Additional: ADC_IN4, CMP_IM4 |
|
|
|
|
Default: PA5 |
PA5 |
11 |
I/O |
|
Alternate: SPI0_SCK, I2S0_CK |
|
|
|
|
Additional: ADC_IN5, CMP_IM5 |
|
|
|
|
Default: PA6 |
|
|
|
|
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, |
PA6 |
12 |
I/O |
|
TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, |
|
|
|
|
CMP_OUT |
|
|
|
|
Additional: ADC_IN6 |
|
|
|
|
Default: PA7 |
|
|
|
|
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, |
PA7 |
13 |
I/O |
|
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, |
|
|
|
|
EVENTOUT |
|
|
|
|
Additional: ADC_IN7 |
|
|
|
|
Default: PB0 |
PB0 |
14 |
I/O |
|
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT |
|
|
|
|
Additional: ADC_IN8 |
PB1 |
15 |
I/O |
|
Default: PB1 Alternate: TIMER2_CH3, TIMER13_CH0, |
Pin Name |
Pins |
Pin Type(1) |
I/O Level(2) |
Functions description |
|
|
|
|
TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 |
VSS |
16 |
P |
|
Default: VSS |
VDD |
17 |
P |
|
Default: VDD |
PA8 |
18 |
I/O |
5VT |
Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT |
PA9(6) |
19 |
I/O |
5VT |
Default: PA9 Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT |
PA10(6) |
20 |
I/O |
5VT |
Default: PA10 Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA |
PA13 |
21 |
I/O |
5VT |
Default: PA13/SWDIO Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) |
PA14 |
22 |
I/O |
5VT |
Default: PA14/SWCLK Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) |
PA15 |
23 |
I/O |
5VT |
Default: PA15 Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT |
PB3 |
24 |
I/O |
5VT |
Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT |
PB4 |
25 |
I/O |
5VT |
Default: PB4 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN |
PB5 |
26 |
I/O |
5VT |
Default: PB5 Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 |
PB6 |
27 |
I/O |
5VT |
Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON |
PB7 |
28 |
I/O |
5VT |
Default: PB7 Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON |
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32E230G4 devices only.
(4)Functions are available on GD32E230G8/6 devices.
(5)Functions are available on GD32E230G8 devices only.
ARM® Cortex®-M23 core
The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M23 processor core
Up to 72 MHz operation frequency
Single-cycle multiplication and hardware divider
Ultra-low power, energy-efficient operation
Excellent code density
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M23 processor is based on the ARMv8-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M23:
Internal Bus Matrix connected with AHB master, Serial Wire Debug Port and Single-cycle IO port
Nested Vectored Interrupt Controller (NVIC)
Breakpoint Unit(BPU)
Data Watchpoint and Trace (DWT)
Serial Wire Debug Port
Embedded memory
Up to 64 Kbytes of Flash memory
Up to 8 Kbytes of SRAM with hardware parity checking
64 Kbytes of inner Flash and 8 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with 0~2 wait states. Table 2-3. GD32E230xx memory map shows the memory map of the GD32E230xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
1.8 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 72 MHz/72 MHz/72 MHz. See Figure 2-8. GD32E230xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.71 V and down to 1.67 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 1.8 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 1.8 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAK range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15 or PA2 and PA3).
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, CMP output, LVD output and USART wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 2 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA
Temperature sensor
One 12-bit 2 MSPS multi-channel ADC is integrated in the device. It has a total of 12 multiplexed channels: up to 10 external channels, 1 channel for internal temperature sensor (VSENSE) and 1 channel for internal reference voltage (VREFINT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timer (TIMER0) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.
DMA
5 channels DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs and I2S
The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.
General-purpose inputs/outputs (GPIOs)
Up to 39 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 39 general purpose I/O pins (GPIO) in GD32E230xx, named PA0 ~ PA15 and PB0 ~ PB15, PC13 ~ PC15, PF0 ~ PF1, PF6 ~ PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push- pull open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.
Timers and PWM generation
One 16-bit advanced timer (TIMER0), up to five 16-bit general timers (TIMER2, TIMER13
~ TIMER16), and one 16-bit basic timer (TIMER5)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels.
It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER2 is based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload up counter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 can also be used as a simple 16-bit time base.
The GD32E230xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.
Calendar with subsecond, second, minute, hour, week day, date, year and month automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler.
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
Supports SAM_V mode
C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.
Serial peripheral interface (SPI)
Up to two SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Separate transmit and receive 32-bit FIFO with DMA capability (only in SPI1)
Data frame size can be 4 to 16 bits (only in SPI1)
Quad-SPI configuration available in master mode (only in SPI1)
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Specially, SPI1 has separate transmit and receive 32- bit FIFO with DMA capability and its data frame size can be 4 to 16 bits. Quad-SPI master mode is also supported in SPI1.
Universal synchronous asynchronous receiver transmitter (USART)
Up to two USARTs with operating frequency up to 4.5 MBits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication.
Inter-IC sound (I2S)
One I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI0
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32E230xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI0. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.
Comparators (CMP)
One fast rail-to-rail low-power comparators with software configurable
Programmable reference voltage (internal or external I/O)
One Comparator (CMP) is implemented within the devices. It can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.
Debug mode
Serial wire debug port
Debug capabilities can be accessed by a debug tool via Serial Wire (SW - Debug Port).
Package and operation temperature
LQFP48 (GD32E230CxTx), LQFP32 (GD32E230KxTx), QFN32 (GD32E230KxUx), QFN28 (GD32E230GxUx), TSSOP20 (GD32E230FxPx) and LGA20 (GD32E230FxVx).
Operation temperature range: -40°C to +85°C (industrial level)
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