这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F107VCT6-GD32 ARM Cortex-M3 Microcontroller

兆易创新GD32F107VCT6-GD32 ARM Cortex-M3 Microcontroller GigaDevice Semiconductor Inc. GD32F107xx ARM® Cortex™-M3 32-bit MCU Datasheet General description The GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F107xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS and an Ethernet MAC. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F107xx devices suitable for a wide range of interconnection applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.   Device information Table 2-1. GD32F107xx devices features and peripheral list   Part Number GD32F107xx   RB RC RD RE RF RG VB VC Flash (KB) 128 256 384 512 768 1024 128 256 SRAM (KB) 96 96 96 96 96 96 96 96 Timers GPTM(16 bit) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4)   Advanced TM(16 bit) 1 (0) 1 (0) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 1 (0) 1 (0)   SysTick 1 1 1 1 1 1 1 1   Basic TM(16 bit) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6)   Watchdog 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 Connectivity U(S)ART 5 5 5 5 5 5 5 5   I2C 1 (0) 1 (0) 2 (0-1) 2 (0-1) 2 (0-1) 2 (0-1) 1 (0) 1 (0)   SPI 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2)   I2S 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2)   CAN 2.0B 2 2 2 2 2 2 2 2   USBFS 1 1 1 1 1 1 1 1   Ethernet MAC 1 1 1 1 1 1 1 1 GPIO 51 51 51 51 51 51 80 80 EXMC 0 0 0 0 0 0 1 1
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F107VCT6-GD32 ARM Cortex-M3 Microcontroller

GigaDevice Semiconductor Inc.
GD32F107xx
ARM® Cortex™-M3 32-bit MCU
Datasheet

General description

The GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F107xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS and an Ethernet MAC.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F107xx devices suitable for a wide range of interconnection applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.
 

Device information

Table 2-1. GD32F107xx devices features and peripheral list

 

Part Number

GD32F107xx

 

RB

RC

RD

RE

RF

RG

VB

VC

Flash (KB)

128

256

384

512

768

1024

128

256

SRAM (KB)

96

96

96

96

96

96

96

96

Timers

GPTM(16

bit)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

 

Advanced

TM(16 bit)

1

(0)

1

(0)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

1

(0)

1

(0)

 

SysTick

1

1

1

1

1

1

1

1

 

Basic TM(16

bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

Watchdog

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

Connectivity

U(S)ART

5

5

5

5

5

5

5

5

 

I2C

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

1

(0)

1

(0)

 

SPI

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

I2S

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

 

CAN 2.0B

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

 

Ethernet

MAC

1

1

1

1

1

1

1

1

GPIO

51

51

51

51

51

51

80

80

EXMC

0

0

0

0

0

0

1

1

EXTI

16

16

16

16

16

16

16

16

ADC

Units

2

2

2

2

2

2

2

2

 

Channels

16

16

16

16

16

16

16

16

DAC

2

2

2

2

2

2

2

2

 

 

Part Number

GD32F107xx

 

VD

VE

VF

VG

ZC

ZD

ZE

ZF

ZG

Flash (KB)

384

512

768

1024

256

384

512

768

1024

SRAM (KB)

96

96

96

96

96

96

96

96

96

Timers

GPTM(16

bit)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

 

Advanced

TM(16 bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

1

1

1

1

1

 

Basic TM(16

bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

U(S)ART

5

5

5

5

5

5

5

5

5

 

I2C

2

2

2

2

2

2

2

2

2

 

SPI

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

 

I2S

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

 

CAN 2.0B

2

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

1

 

Ethernet

MAC

1

1

1

1

1

1

1

1

1

GPIO

80

80

80

80

112

112

112

112

112

EXMC

1

1

1

1

1

1

1

1

1

EXTI

16

16

16

16

16

16

16

16

16

ADC

Units

2

2

2

2

2

2

2

2

2

 

Channels

16

16

16

16

16

16

16

16

16

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP100

LQFP144

 

Memory map

Table 2-3. GD32F107xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

External

device

 

 

 

 

AHB

 

0xA000 0000 - 0xA000 0FFF

 

EXMC - SWREG

 

 

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC -

NOR/PSRAM/SRA M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

Reserved

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

Reserved

 

 

0x4002 6000 - 0x4002 63FF

Reserved

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

Reserved

 

 

0x4002 3C00 - 0x4002 3FFF

Reserved

 

 

0x4002 3800 - 0x4002 3BFF

Reserved

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2C00 - 0x4002 2FFF

Reserved

 

 

0x4002 2800 - 0x4002 2BFF

Reserved

 

 

0x4002 2400 - 0x4002 27FF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1C00 - 0x4002 1FFF

Reserved

 

 

0x4002 1800 - 0x4002 1BFF

Reserved

 

 

0x4002 1400 - 0x4002 17FF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0C00 - 0x4002 0FFF

Reserved

 

 

0x4002 0800 - 0x4002 0BFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA1

 

 

0x4002 0000 - 0x4002 03FF

DMA0

 

 

0x4001 8400 - 0x4001 FFFF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 8000 - 0x4001 83FF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 7C00 - 0x4001 7FFF

Reserved

 

 

0x4001 7800 - 0x4001 7BFF

Reserved

 

 

0x4001 7400 - 0x4001 77FF

Reserved

 

 

0x4001 7000 - 0x4001 73FF

Reserved

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5C00 - 0x4001 67FF

Reserved

 

 

0x4001 5800 - 0x4001 5BFF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

Reserved

 

 

0x4001 5000 - 0x4001 53FF

Reserved

 

 

0x4001 4C00 - 0x4001 4FFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

Reserved

 

 

0x4001 4400 - 0x4001 47FF

Reserved

 

 

0x4001 4000 - 0x4001 43FF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

Reserved

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

 

0x4000 6000 - 0x4000 63FF

Shared CAN SRAM

512 bytes

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

Reserved

 

 

0x4000 1C00 - 0x4000 1FFF

Reserved

 

 

0x4000 1800 - 0x4000 1BFF

Reserved

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

 

 

SRAM

 

 

 

 

 

AHB

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2006 0000 - 0x2006 FFFF

Reserved

 

 

0x2003 0000 - 0x2005 FFFF

Reserved

 

 

0x2002 0000 - 0x2002 FFFF

Reserved

 

 

0x2001 C000 - 0x2001 FFFF

Reserved

 

 

0x2001 8000 - 0x2001 BFFF

Reserved

 

 

0x2000 5000 - 0x2001 7FFF

 

SRAM

 

 

0x2000 0000 - 0x2000 4FFF

 

 

Code

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF F000 - 0x1FFF F7FF

Boot loader

 

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

 

0x1FFF C010 - 0x1FFF EFFF

 

0x1FFF C000 - 0x1FFF C00F

0x1FFF B000 - 0x1FFF BFFF

0x1FFF 7A10 - 0x1FFF AFFF

Reserved

0x1FFF 7800 - 0x1FFF 7A0F

Reserved

0x1FFF 0000 - 0x1FFF 77FF

Reserved

0x1FFE C010 - 0x1FFE FFFF

Reserved

0x1FFE C000 - 0x1FFE C00F

Reserved

0x1001 0000 - 0x1FFE BFFF

Reserved

0x1000 0000 - 0x1000 FFFF

Reserved

0x083C 0000 - 0x0FFF FFFF

Reserved

0x0830 0000 - 0x083B FFFF

Reserved

0x0810 0000 - 0x082F FFFF

 

Main Flash

0x0802 0000 - 0x080F FFFF

0x0800 0000 - 0x0801 FFFF

0x0030 0000 - 0x07FF FFFF

Reserved

0x0010 0000 - 0x002F FFFF

 

Aliased to Main Flash or Boot loader

0x0002 0000 - 0x000F FFFF

0x0000 0000 - 0x0001 FFFF

 

GD32F107Zx LQFP144 pin definitions

Table 2-4. GD32F107Zx LQFP144 pin definitions

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4 Alternate:TRACED1, EXMC_A20

 

PE5

 

4

 

I/O

 

5VT

Default: PE5 Alternate:TRACED2, EXMC_A21

 

PE6

 

5

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3, EXMC_A22

VBAT

6

P

 

Default: VBAT

PC13-

TAMPER- RTC

 

7

 

I/O

 

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

 

8

 

I/O

 

Default: PC14 Alternate: OSC32IN

PC15- OSC32OUT

 

9

 

I/O

 

Default: PC15 Alternate: OSC32OUT

 

PF0

 

10

 

I/O

 

5VT

Default: PF0 Alternate: EXMC_A0

 

PF1

 

11

 

I/O

 

5VT

Default: PF1

Alternate: EXMC_A1

 

PF2

 

12

 

I/O

 

5VT

Default: PF2

Alternate: EXMC_A2

 

PF3

 

13

 

I/O

 

5VT

Default: PF3

Alternate: EXMC_A3

 

PF4

 

14

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4

 

PF5

 

15

 

I/O

 

5VT

Default: PF5 Alternate: EXMC_A5

VSS_5

16

P

 

Default: VSS_5

VDD_5

17

P

 

Default: VDD_5

PF6

18

I/O

 

Default: PF6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_NIORD

PF7

19

I/O

 

Default: PF7

 

 

 

 

Alternate: EXMC_NREG

PF8

20

I/O

 

Default: PF8

 

 

 

 

Alternate: EXMC_NIOWR

PF9

21

I/O

 

Default: PF9

 

 

 

 

Alternate: EXMC_CD

PF10

22

I/O

 

Default: PF10

 

 

 

 

Alternate: EXMC_INTR

OSCIN

23

I

 

Default: OSCIN

 

 

 

 

Remap: PD0

OSCOUT

24

O

 

Default: OSCOUT

 

 

 

 

Remap: PD1

NRST

25

I/O

 

Default: NRST

PC0

26

I/O

 

Default: PC0

 

 

 

 

Alternate: ADC01_IN10

 

 

 

 

Default: PC1

PC1

27

I/O

 

Alternate: ADC01_IN11, ETH_MII_MDC,

 

 

 

 

ETH_RMII_MDC

PC2

28

I/O

 

Default: PC2

 

 

 

 

Alternate: ADC01_IN12, ETH_MII_TXD2

PC3

29

I/O

 

Default: PC3

 

 

 

 

Alternate: ADC01_IN13, ETH_MII_TX_CLK

VSSA

30

P

 

Default: VSSA

VREF-

31

P

 

Default: VREF-

VREF+

32

P

 

Default: VREF+

VDDA

33

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

34

I/O

 

Alternate: WKUP, USART1_CTS, ADC01_IN0,

TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,

 

 

 

 

TIMER7_ETI, ETH_MII_CRS

 

 

 

 

Default: PA1

PA1

35

I/O

 

Alternate: USART1_RTS, ADC01_IN1,

TIMER1_CH1, TIMER4_CH1,

 

 

 

 

ETH_MII_RX_CLK, ETH_RMII_REF_CLK

 

 

 

 

Default: PA2

PA2

36

I/O

 

Alternate: USART1_TX, ADC01_IN2,

TIMER1_CH2, TIMER4_CH2, ETH_MII_MDIO,

 

 

 

 

ETH_RMII_MDIO

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Default: PA3

PA3

37

I/O

 

Alternate: USART1_RX, ADC01_IN3,

 

 

 

 

TIMER1_CH3, TIMER4_CH3, ETH_MII_COL

VSS_4

38

P

 

Default: VSS_4

VDD_4

39

P

 

Default: VDD_4

 

 

 

 

Default: PA4

PA4

40

I/O

 

Alternate: SPI0_NSS, USART1_CK,

ADC01_IN4, DAC_OUT0

 

 

 

 

Remap:SPI2_NSS, I2S2_WS

PA5

41

I/O

 

Default: PA5

 

 

 

 

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

 

 

 

 

Default: PA6

PA6

42

I/O

 

Alternate: SPI0_MISO, ADC01_IN6,

TIMER2_CH0, TIMER7_BKIN

 

 

 

 

Remap: TIMER0_BKIN

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, ADC01_IN7,

PA7

43

I/O

 

TIMER2_CH1, TIMER7_CH0_ON,

 

 

 

 

ETH_MII_RX_DV, ETH_RMII_CRS_DV

 

 

 

 

Remap: TIMER0_CH0_ON

 

 

 

 

Default: PC4

PC4

44

I/O

 

Alternate: ADC01_IN14, ETH_MII_RXD0,

 

 

 

 

ETH_RMII_RXD0

 

 

 

 

Default: PC5

PC5

45

I/O

 

Alternate: ADC01_IN15, ETH_MII_RXD1,

 

 

 

 

ETH_RMII_RXD1

 

 

 

 

Default: PB0

PB0

46

I/O

 

Alternate: ADC01_IN8, TIMER2_CH2,

TIMER7_CH1_ON, ETH_MII_RXD2

 

 

 

 

Remap: TIMER0_CH1_ON

 

 

 

 

Default: PB1

PB1

47

I/O

 

Alternate: ADC01_IN9, TIMER2_CH3,

TIMER7_CH2_ON, ETH_MII_RXD3

 

 

 

 

Remap: TIMER0_CH2_ON

PB2

48

I/O

5VT

Default: PB2, BOOT1

PF11

49

I/O

5VT

Default: PF11

 

 

 

 

Alternate: EXMC_NIOS16

PF12

50

I/O

5VT

Default: PF12

 

 

 

 

Alternate: EXMC_A6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VSS_6

51

P

 

Default: VSS_6

VDD_6

52

P

 

Default: VDD_6

 

PF13

 

53

 

I/O

 

5VT

Default: PF13 Alternate: EXMC_A7

 

PF14

 

54

 

I/O

 

5VT

Default: PF14

Alternate: EXMC_A8

 

PF15

 

55

 

I/O

 

5VT

Default: PF15 Alternate: EXMC_A9

 

PG0

 

56

 

I/O

 

5VT

Default: PG0 Alternate: EXMC_A10

 

PG1

 

57

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11

 

PE7

 

58

 

I/O

 

5VT

Default: PE7 Alternate: EXMC_D4 Remap: TIMER0_ETI

 

PE8

 

59

 

I/O

 

5VT

Default: PE8 Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

 

PE9

 

60

 

I/O

 

5VT

Default: PE9 Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

61

P

 

Default: VSS_7

VDD_7

62

P

 

Default: VDD_7

 

PE10

 

63

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

PE11

 

64

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8 Remap: TIMER0_CH1

 

PE12

 

65

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

 

PE13

 

66

 

I/O

 

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2

 

PE14

 

67

 

I/O

 

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3

PE15

68

I/O

5VT

Default: PE15

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_D12

Remap: TIMER0_BKIN

 

 

PB10

 

 

69

 

 

I/O

 

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX, ETH_MII_RX_ER

Remap: TIMER1_CH2

 

 

PB11

 

 

70

 

 

I/O

 

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX, ETH_MII_TX_EN, ETH_RMII_TX_EN

Remap: TIMER1_CH3

VSS_1

71

P

 

Default: VSS_1

VDD_1

72

P

 

Default: VDD_1

 

 

PB12

 

 

73

 

 

I/O

 

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, I2S1_WS, CAN1_RX, ETH_MII_TXD0, ETH_RMII_TXD0

 

 

PB13

 

 

74

 

 

I/O

 

 

5VT

Default: PB13

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX, ETH_MII_TXD1, ETH_RMII_TXD1

 

PB14

 

75

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON

 

PB15

 

76

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD

 

 

PD8

 

 

77

 

 

I/O

 

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX, ETH_MII_RX_DV,

ETH_RMII_CRS_DV

 

 

PD9

 

 

78

 

 

I/O

 

 

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX, ETH_MII_RXD0,

ETH_RMII_RXD0

 

 

PD10

 

 

79

 

 

I/O

 

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, ETH_MII_RXD1,

ETH_RMII_RXD1

PD11

80

I/O

5VT

Default: PD11

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_A16

Remap: USART2_CTS, ETH_MII_RXD2

 

 

PD12

 

 

81

 

 

I/O

 

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS,

ETH_MII_RXD3

 

PD13

 

82

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18 Remap: TIMER3_CH1

VSS_8

83

P

 

Default: VSS_8

VDD_8

84

P

 

Default: VDD_8

 

PD14

 

85

 

I/O

 

5VT

Default: PD14 Alternate: EXMC_D0

Remap: TIMER3_CH2

 

PD15

 

86

 

I/O

 

5VT

Default: PD15 Alternate: EXMC_D1 Remap: TIMER3_CH3

 

PG2

 

87

 

I/O

 

5VT

Default: PG2 Alternate: EXMC_A12

 

PG3

 

88

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13

 

PG4

 

89

 

I/O

 

5VT

Default: PG4

Alternate: EXMC_A14

 

PG5

 

90

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15

 

PG6

 

91

 

I/O

 

5VT

Default: PG6

Alternate: EXMC_INT1

 

PG7

 

92

 

I/O

 

5VT

Default: PG7 Alternate: EXMC_INT2

PG8

93

I/O

5VT

Default: PG8

VSS_9

94

P

 

Default: VSS_9

VDD_9

95

P

 

Default: VDD_9

 

PC6

 

96

 

I/O

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

 

PC7

 

97

 

I/O

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

PC8

98

I/O

5VT

Default: PC8

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: TIMER7_CH2

Remap: TIMER2_CH2

 

PC9

 

99

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

 

PA8

 

100

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF

 

PA9

 

101

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

 

PA10

 

102

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

 

PA11

 

103

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

 

PA12

 

104

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

 

PA13

 

105

 

I/O

 

5VT

Default: JTMS, SWDIO Remap: PA13

NC

106

 

 

-

VSS_2

107

P

 

Default: VSS_2

VDD_2

108

P

 

Default: VDD_2

 

PA14

 

109

 

I/O

 

5VT

Default: JTCK, SWCLK

Remap: PA14

 

 

PA15

 

 

110

 

 

I/O

 

 

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

111

 

I/O

 

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

 

PC11

 

112

 

I/O

 

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

 

PC12

 

113

 

I/O

 

5VT

Default: PC12 Alternate: UART4_TX

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

114

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2 Remap: CAN0_RX

 

PD1

 

115

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX

 

PD2

 

116

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

 

PD3

 

117

 

I/O

 

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS

 

PD4

 

118

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

119

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

VSS_10

120

 

 

Default: VSS_10

VDD_10

121

 

 

Default: VDD_10

 

PD6

 

122

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT Remap: USART1_RX

 

PD7

 

123

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

124

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2

 

PG10

 

125

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2

 

PG11

 

126

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1

 

PG12

 

127

 

I/O

 

5VT

Default: PG12 Alternate: EXMC_NE3

 

PG13

 

128

 

I/O

 

5VT

Default: PG13

Alternate: EXMC_A24

 

PG14

 

129

 

I/O

 

5VT

Default: PG14

Alternate: EXMC_A25

VSS_11

130

P

 

Default: VSS_11

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VDD_11

131

P

 

Default: VDD_11

PG15

132

I/O

5VT

Default: PG15

 

 

PB3

 

 

133

 

 

I/O

 

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1,

SPI0_SCK

 

PB4

 

134

 

I/O

 

5VT

Default: NJTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

 

PB5

 

 

135

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD, ETH_PPS_OUT

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

 

PB6

 

136

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX

 

 

PB7

 

 

137

 

 

I/O

 

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV

Remap: USART0_RX

BOOT0

138

I

 

Default: BOOT0

 

PB8

 

139

 

I/O

 

5VT

Default: PB8

Alternate: TIMER3_CH2, ETH_MII_TXD3 Remap: I2C0_SCL, CAN0_RX

 

PB9

 

140

 

I/O

 

5VT

Default: PB9

Alternate: TIMER3_CH3 Remap: I2C0_SDA, CAN0_TX

PE0

141

I/O

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0

PE1

142

I/O

5VT

Default: PE1

Alternate: EXMC_NBL1

VSS_3

143

P

 

Default: VSS_3

VDD_3

144

P

 

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.

ARM® Cortex™-M3 core

The Cortex™-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex™-M3 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 1024 Kbytes of Flash memory
96 Kbytes of SRAM

The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash at most and 96 Kbytes of inner SRAM is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Table 2-3. GD32F107xx memory map shows the memory map of the GD32F107xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low- speed APB domain is 54 MHz. See Figure 2-5. GD32F107xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6), USBFS in device mode (PA9, PA11 and PA12). It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by

setting a bit in option bytes.


Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC engine
Up to 1 MSPS conversion rate
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to two 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general-purpose timers (TIMERx) and the advanced-control timers (TIMER0 and TIMER7) with internal connection. The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage

into a digital value.


Digital to analog converter (DAC)

Two 12-bit DAC converters of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The two 12-bit buffered DAC channels are used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.

DMA

7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S
Dedicated DMA controller with the Ethernet application

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable

There are up to 112 general purpose I/O pins (GPIO) in GD32F107xx, named PA0 ~ PA15 and  PB0  ~ PB15,  PC0  ~  PC15,  PD0  ~ PD15,  PE0  ~  PE15,  PF0-PF15,  PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are

shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Up to two 16-bit advanced-control timer (TIMER0 & TIMER7), four 16-bit general-purpose timers (GPTM), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each GPTM and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced-control timer (TIMER0 & TIMER7) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead- time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for
Input capture
Output compare
PWM generation (edge- or center-aligned counting modes)
Single pulse mode output

If configured as a general-purpose 16-bit timer, it has the same functions as the TIMER x timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), known as TIMER1 ~ TIMER4 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The GPTM also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F107xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.

The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART4.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F107xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error.

Universal serial bus full-speed (USBFS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for USB CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Ethernet MAC interface

IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 17 with 25 MHz output and RMII up to 9 with 50 MHz output. The function of 32-bit CRC checking is also available.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and

CF card
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F107Zx), LQFP100 (GD32F107Vx), LQFP64 (GD32F107Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

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发布时间: : 2022-01--14
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发布时间: : 2022-02--07
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自组网无线模块WiFi乐鑫esp32 c3芯片模组matter物联网工程项目

发布时间: : 2022-11--28
自组网无线模块WiFi乐鑫esp32 c3芯片模组matter物联网工程项目介绍,和学习游泳一样,学习物联网,仅仅了解理论知识是远远不够的,还需实际“下水”,动手实现物联网工程项目才能真正掌握物联网技术。除此之外,当工程项目走向产品的量产阶段时,还需要考虑网络连接、配置、物联网云平台交互固件管理和升级、量产管理、安全配置等多方面因素。 在开发一个完整的物联网工程项目时,我们需要注意哪些方面呢?自组网无线模块WiFi乐鑫esp32 c3芯片模组matter应用在智能家居是常见的物联网应用场景之一,而智能灯又是智能家居中很基础且实用的家电之一,可以应用在家庭、酒店、体育馆、医院、道路等场所,因此以自组网无线模块WiFi乐鑫esp32 c3芯片模组搭建智能照明工程为切入点逐步对该工程项目的基本组成、可实现功能等进行阐述,并给出相对完整的工程项目开发指导。希望以此项目为参考,做到举一反三,构建丰富多彩的物联网应用。 典型的物联网工程项目介绍 从开发的角度来看,可以将物联网工程项目简单地分为物联网设备的软件开发和硬件开发用户端应用程序开发、物联网云平台开发等基础功能模块。明确基础功能模块是十分重要。 1、常见物联网设备的基本模块 物联网设备的软件开发和硬件开发主要包括以下基本模块: 数据采集。作为物联网体系结构的底层,感知控制层中的物联网设备通过所用芯片及其外设将不同的传感器和设备连接起来,可实现数据采集、运行控制等功能。 用户绑定与初始化配置。在大多数物联网设备中,用户绑定与初始化配置是在一个操作流程中完成的,如可通过配置 Wi-Fi 网络来建立用户和设备之间的绑定关系。 自组网无线模块WiFi乐鑫esp32 c3芯片模组matter与物联网云平台交互。为了实现对物联网设备的监控、控制功能,还需要将物联网设备连接到物联网云平台,通过与物联网云平台的交互来实现运行控制、状态上报等功能。 设备控制。设备通过与物联网云平台建立网络连接,可实现和云端的通信,完成设备注册、绑定、控制等功能。用户可以通过物联网云平台或本地通信协议,在智能手机 App 上完成产品的状态查询与操作。 固件更新。自组网无线模块WiFi乐鑫esp32 c3芯片模组matter物联网设备还可以根据设备厂商的需求完成固件更新。通过接收云端发送的固件更新命令,可以实现固件更新和版本管理。通过固件更新功能可不断完善物联网设备的功能修复缺陷,提升用户体验。 2、用户端应用程序基本模块 用户端应用程序(如智能手机 App) 主要包括以下基本模块: 账户体系与授权。支持账户与设备授权。 设备控制。智能手机 App 通常具有控制设备的功能,用户可轻松便捷地通过智能手机连接物联网设备,通过智能手机 App 随时随地控制、管理物联网设备。其实,在实际的智能家居中,设备主要是通过智能手机 App 来进行控制的,这样不仅可以实现设备的智能化管理,还可以节省人力的支出,所以设备控制是必需的功能,如设备功能属性控制、场景控制、时间设定远程控制、设备联动等。自组网无线模块WiFi乐鑫esp32 c3芯片模组matter智能家居的用户还可以根据个人需求来设置个性化的场景,对照明、家电、门禁等进行控制,让用户的家居生活更加舒适、便利,如定时开关空调、远程关闭空调、打开门锁时玄关灯联动开启、一键开启“影院”模式等。消息通知。该功能可将物联网设备运行状态的各项数据实时地反馈到智能手机 App 上,当物联网设备出现异常时,可远程向智能手机 App 发送报警信息。 售后客服。智能手机 App 可以提供产品的售后服务,从而及时为用户解决物联网设备故障和技术操作等相关问题。 特色功能。自组网无线模块WiFi乐鑫esp32 c3芯片模组为了满足不同用户的需求,还可增加一些实用的功能,如摇一摇、NFC、GPS 等GPS 功能可根据地点、距离来设定场景执行的精度;摇一摇功能则可通过摇一摇来设定设备或场景所要完成的命令。
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25
2022-11

全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅谈物联网

发布时间: : 2022-11--25
全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅谈物联网,在20世纪末,随着计算机网络和通信技术的兴起,互联网以迅雷不及掩耳之势融入了人们的生活。随着互联网技术不断成熟,又延伸出了物联网的概念。物联网的英文为 Internet of Thing(IoT),从字面意义来看,物联网就是物物相连的互联网。如果说互联网打破了空间和时间的限制,极大地拉近了“人与人”之间的距离,物联网则让“物”成为重要的参与者,极大地拉近“人与物”“物与物”的距离。 2021 年发布的“十四五”规划和《物联网新型基础设施建设三年行动计划(2021-2023 年)》为物联网产业注入了新动力。在可预见的未来内,物联网必定成为信息产业的驱动力。全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅为您讲解什么是物联网呢? 要想准确地给出物联网的定义并不是容易的事情,因为物联网的涵义和外延都在不停发展变化中。早在 1995 年,比尔·盖茨在其著作《The Road Ahead》中就率先提出了物联网的概念。简单来说,物联网利用互联网让物体相互交换信息,终达到“万物互联的目标,这是早期对物联网概念的阐述,也是对未来科技的幻想。随着经济和科技的快速发展,20多年前的幻想正在走进现实中。从各类智能设备、智能家居、智慧城市、车联网、可穿戴设备等,到物联网技术成为“元宇宙”的支撑,新的概念还在源源不断地涌现。对物联网的体系结构进行介绍,再对常见的物联网应用——智能家居进行阐述,以便帮助建立对物联网的清晰认知。 1.1 物联网的体系结构 物联网涉及多项技术,这些技术在不同的行业有不同的应用需求和形态。为了梳理物联网的体系结构、关键技术和应用特点,需要建立统一的体系结构和标准的技术体系。将物联网的体系结构简单地分为感知控制层、网络层、平台层、应用层。 1.感知控制层 感知控制层是实现物联网全面感知的核心层,也是物联网体系结构中基础的一层,其主要功能是实现对信息的采集、识别和控制。感知控制层由具有感知、识别、控制和执行等能的多种设备组成,负责对物质属性、行为态势、设备状态等各类数据进行获取与状态辨识。 完成对现实物理世界的认知和识别。感知控制层还能对设备状态等进行控制。在感知控制层中,常见的设备就是各类传感器,这些传感器起到对信息采集和识别的重要作用。传感器好比人类的感觉器官,如光敏传感器好比人类的视觉、声敏传感器好比听觉、气敏传感器好比嗅觉,而压敏、温敏等传感器好比触觉,有了“感官”的物体就慢慢变得“活起来,并实现了对物理世界的智能感知、识别和操作。 2.网络层 网络层的主要功能是实现信息的传输和通信,既负责将从感知控制层获得的数据传输到指定的地方,还负责将应用层下发的控制命令传输到感知控制层,是连接感知控制层和平台层的重要通信桥梁。物联网中的“网”字有以下两个含义:物接入互联网和互联网传输。 1)物接入互联网互联网实现了人与人之间的互联互通,但在互联网中人与物或物与物之间无法互联。在物联网出现前,大部分的物是不具有联网能力的。全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅随着技术的不断发展,物联网将物连接到了互联网,实现了人与物、物与物的互联。目前,物接入互联网通常使用两种方式:一种是有线网络接入;另一种是无线网络接入。 有线网络接入方式包括以太网、串行通信(如 RS-232、RS-485)和 USB 等。无线网络接入方式采用的是无线通信,无线通信又分为短距离无线通信和长距离无线通信。短距离无线通信主要包括 ZigBee、Bluetooth Wi-Fi、NFC(Near-Field Communication)、RFID(Radio Frequency Identification)等。全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅长距离无线通信主要包括 MTC (enhanced Machine TypeCommunication)、LoRa、NB-IoT (Narrow Band Interet of Things)、2G、3G、4G、5G 等 2)互联网传输确定物接入互联网的方式,相当于确定了数据的物理传输链路,之后还需要确定使用哪些通信协议来传输数据。与互联网的终端相比,目前大部分物联网终端的可用资源较少,如处理性能、存储容量、网络速率等,因此在物联网应用中需要选择占用资源更少的通信协议。现在广泛使用的通信协议有两种:MQTT (Message Queuing Telemetry Transport)和 CoAF(Constrained Application Protocol)。 3.平台层 平台层主要指物联网云平台。当所有的物联网终端联网后,数据需要汇总在一个物联网云平台上,实现对终端状态数据的计算、存储。平台层主要为物联网应用提供支撑,提供海量设备的接入与管理能力,可以将物联网终端连接到物联网云平台,支撑终端数据采集上云,以及从云端向终端下发命令,从而进行远程控制。平台层作为承接设备与行业应用的中间服务在整个物联网体系结构中起着承上启下的作用,全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅承载了抽象化的业务逻辑和标准化的核心数据模型,不仅可以实现设备的快速接入,还可以提供强大的模块化能力,能够满足行业应用场景下的各类需求。平台层主要包含设备接入、设备管理、安全管理、消息通信、监控运维和数据应用等功能模块。 设备管理:包含设备创建、设备维护、数据转换、数据同步、设备分布等功能,设备接入:实现终端与物联网云平台的连接、通信。安全管理:从安全认证和通信安全两个方面来保证物联网数据传输的安全。消息通信:包括 3种信息传输方式,即终端向物联网云平台发送数据、物联网云平台将数据发送到服务器端或其他物联网云平台,以及服务器端的远程控制设备。监控运维:涉及监控诊断、固件更新、在线调试、日志服务等。数据应用:涉及数据的存储、分析和应用。 4.应用层 应用层利用平台层处理后的信息来管理应用程序,应用层使用数据库、分析软件等工具对平台层的数据进行过滤和处理。应用层的结果和数据可用于真实的物联网应用,如智慧医疗、智能农业、智能家居和智能城市等。 当然,物联网的体系结构还可以再细分出更多的层次,但无论分为多少个层次,其背后的原理都万变不离其宗。了解物联网的体系结构有助于加深对物联网技术的理解和构建功能完整的物联网工程。 1.2物联网应用之智能家居 物联网的应用已经渗透到了各行各业,和人们生活息息相关的物联网应用就要数智能家居了。很多传统家居已经使用了一件或多件物联网设备,许多新建住宅从一开始就采用物联网技术进行设计。 目前,全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅智能家居发展阶段可以简单地划分为智能产品阶段、场景互联阶段和智能阶段。 一个阶段为智能产品阶段。与传统家居不同,在智能家居中,物联网设备通过感知技术接收信号,通过 Wi-Fi、Bluetooth LE(低功耗蓝牙)和 ZigBee 等无线通信技术联网,用户可以通过多种多样的方式来控制智能产品,如智能手机 App、语音助手、智能音箱控制等。 第二个阶段为场景互联阶段。这个阶段不再是简单控制某个智能产品,而是使两个或者多个智能产品进行互联互通,在一定程度上实现自动化,全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅形成一个自定义的场景模式。例如,当用户按下任意场景模式按键时就可以按预先设定的场景模式开启灯光、窗帘、空调等智能家居设备。当然,其前提条件是要设置好联动的逻辑,包括触发条件和执行动作。想象一下当室内的温度低于 10℃ 时,触发空调制热模式,在早上7 点时,播放用于唤醒用户的背景音乐,伴随着音乐自动打开智能窗帘,电饭煲或面包机通过智能插座自动开始工作:在起床洗漱的同时,早餐就准备好了,不耽误上班的时间,生活变得更加方便了。 第三个阶段为智能阶段。随着接入的智能家居设备的增多,产生的各类数据也会增多。借助于云计算、大数据和人工智能,智能家居就如同安装了“更加智慧的大脑”,已经不需要主人频繁发出命令了。智能家居会从之前的交互中收集数据并学习主人的行为模式和喜好,自动处理事务,包括提供用于决策的建议。 现在,大多数智能家居正处于场景联动阶段。随着智能产品渗透率和智能化的提高,通信协议之间壁垒正在被不断打破。在未来,全网白菜价乐鑫esp32 c3芯片模组总代理飞睿科技浅智能家居一定能够实现真正的“智能”,正如电影《钢铁侠》中智能系统贾维斯(Jarvis),不仅能帮主人控制各种设备、处理日常事务,还具有超强的计算能力和思考能力。在智能阶段,人们将获取数量更多、质量更高的服务体验。
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24
2022-11

低功耗2.4G/5.8G无线模块芯片头盔儿童座椅应用

发布时间: : 2022-11--24
低功耗2.4G/5.8G无线模块芯片头盔儿童座椅应用,物联网的今天,人们在生活中随处可见的产品很多都是应用了2.4G/5.8G无线模块。比如无线遥控器、智能家居、玩具控制、健康监测、标签读写器等等。那么低功耗2.4G/5.8G无线模块芯片行业的未来前景如何? 科技的不断发展,以及人们生活水平的不断上升,无线的优点已经逐步显现。有线通信会有道地理的限制、需要较长的相应时间,而无线技术几乎不受到地理环境的限制,可以在短时间内组建通信链路。它具有保密性高、抗干扰能力强、体积小巧、传输距离远、双向双工、功耗小、传输宽带大的优点。随着低功耗2.4G/5.8G无线模块芯片技术的不断发展和成熟,无线模块将被广泛应用于生活、工业、医疗等行业。 随着全球电子制造行业逐步向中国大陆转移,电子行业集群效益在中国逐步显现,中国不少厂商生产经营无线模块,加速推动了中国成为电子产业的制造中心和消费中心。全球主要的电子品牌纷纷进入我国,与品牌商提供配套的代工服务商也纷纷在我国设厂,这样大大促进了低功耗2.4G/5.8G无线模块芯片在中国的发展,并且随着技术的不断改进,中国的无线模块逐步涵盖产品价值链的环节。 因此,低功耗2.4G/5.8G无线模块芯片行业的未来前景发展应该还是很不错的,无线模块是高技术装备,用户企业选择和配套厂家后一般不轻易更换,后期的产品维护也是由厂家负责。随着技术的不断发展,未来将会有更多的领域用到无线模块,并且将有更多的厂家生产。 低功耗2.4G/5.8G无线模块芯片无线模块定制方案-智能头盔 随着人们生活水平的提高,越来越多的人开始注重健康这一块了,跑步和骑行则是经济实惠的健康运动方式。对于喜欢骑行的运动者来说,安全尤为重要,骑行的过程中有时很枯燥,那么智能头盔因此而衍生,它内置无线模块,可通过蓝牙于手机相连可播放音乐,让骑行之路更舒心。 智能头盔拥有普通头盔所没有的功能,不仅符合自行车运动的需求,而且它是一款智能可穿戴产品。非常方便骑行时听音乐,头盔上放置无线模块,可以将手机里的音乐通过头盔传到耳朵,因此骑行者骑车听歌再也不用把耳机塞进耳朵,非常的方便实用。 在车把上有个调节器可以轻松调节音乐声音大小,还可以切换上一曲、下一曲音乐,除了播放音乐,智能头盔通过蓝牙与手机APP连接,能够进行打电话、语音导航等操作,还可以利用手机上的APP随时查看骑行情况和具体的信息。 低功耗2.4G/5.8G无线模块芯片无线蓝牙模块应用儿童安全座椅 不管是在电视上还是在真实的生活中,经常上演着小孩子在车里面因为好动而受伤,还有的可能因为其它的原因被甩出车外而造成重伤甚至死亡,儿童安全问题一直是人们比较关注的问题,在儿童安全座椅上安装无线蓝牙模块,通过手机来无线控制,给儿童安全问题增添了一层保护锁。 近期,一家生产儿童安全座椅的厂家通过网站找到了我们,他们想要做一款车载安全座椅手机遥控器,需要找一款能与手机互相通信并且有串口的无线蓝牙模块,因为他的产品外部还有一块控制板,做座椅的智能检测及控制,主要是需要通过低功耗2.4G/5.8G无线模块芯片蓝牙模块的模组进行数据传输,因此想要一款传输性能相对稳定的无线蓝牙模块。通过和工程师的一番电话沟通后,现有的无线蓝牙模块完全符合客户的需求,客户很满意直接下单两百个回去试产,还说后续如果试产成功将会长期合作。 影响低功耗2.4G/5.8G无线模块芯片通讯的两大因素及解决方法 在物联网的今天,越来越多的无线模块产品出现在人们的生活和工作中,企业在实际的生产中会碰到各种各样的因素影响到无线模块的正常通讯,那么这些因素到底有哪些,又该怎么去避免呢? 1.环境因素干扰 一般作业现场的工作环境大多不符合精密仪器的运行条件,有些粉尘较多的车间工作环境对于电子产品的运行稳定性和使用寿命有着严重的影响。可以通过终端箱体封闭设计,尽可能地隔离外界环境,使得内部仪器处于稳定的工作环境。外置天线来规避环境所造成的干扰问题。 2.存在人为干扰因素 人为产生的电磁干扰根本原因是导体中有电压或电流的变化,即较大dv/dt能够使导体产生电磁波辐射。由于导体中的dv/dt或di/at会产生伴随电磁辐射。会对电磁环境造成污染。凡是有电压电流突变的场合,肯定会有电磁干扰存在。可以通过将低功耗2.4G/5.8G无线模块芯片通讯终端做成一个装置,也就是箱体结构。无线设备起到的不仅仅是传输效果,也包含了数据处理能力,自己可以形成一套完整且独立的系统。外部电路与无线通讯装置均采用了完善的隔离电路,保证将外部电路包括容性的干扰到对终端内部电路的运行降到低。
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