这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F107VGT6-GD32 ARM Cortex-M3 Microcontroller

兆易创新GD32F107VGT6-GD32 ARM Cortex-M3 Microcontroller GigaDevice Semiconductor Inc. GD32F107xx ARM® Cortex™-M3 32-bit MCU Datasheet General description The GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F107xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS and an Ethernet MAC. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F107xx devices suitable for a wide range of interconnection applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.   Device information Table 2-1. GD32F107xx devices features and peripheral list   Part Number GD32F107xx   RB RC RD RE RF RG VB VC Flash (KB) 128 256 384 512 768 1024 128 256 SRAM (KB) 96 96 96 96 96 96 96 96 Timers GPTM(16 bit) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4)   Advanced TM(16 bit) 1 (0) 1 (0) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 1 (0) 1 (0)   SysTick 1 1 1 1 1 1 1 1   Basic TM(16 bit) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6)   Watchdog 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 Connectivity U(S)ART 5 5 5 5 5 5 5 5   I2C 1 (0) 1 (0) 2 (0-1) 2 (0-1) 2 (0-1) 2 (0-1) 1 (0) 1 (0)   SPI 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2)   I2S 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2)   CAN 2.0B 2 2 2 2 2 2 2 2   USBFS 1 1 1 1 1 1 1 1   Ethernet MAC 1 1 1 1 1 1 1 1 GPIO 51 51 51 51 51 51 80 80 EXMC 0 0 0 0 0 0 1 1
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F107VGT6-GD32 ARM Cortex-M3 Microcontroller

GigaDevice Semiconductor Inc.
GD32F107xx
ARM® Cortex™-M3 32-bit MCU
Datasheet

General description

The GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F107xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS and an Ethernet MAC.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F107xx devices suitable for a wide range of interconnection applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.
 

Device information

Table 2-1. GD32F107xx devices features and peripheral list

 

Part Number

GD32F107xx

 

RB

RC

RD

RE

RF

RG

VB

VC

Flash (KB)

128

256

384

512

768

1024

128

256

SRAM (KB)

96

96

96

96

96

96

96

96

Timers

GPTM(16

bit)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

 

Advanced

TM(16 bit)

1

(0)

1

(0)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

1

(0)

1

(0)

 

SysTick

1

1

1

1

1

1

1

1

 

Basic TM(16

bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

Watchdog

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

Connectivity

U(S)ART

5

5

5

5

5

5

5

5

 

I2C

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

1

(0)

1

(0)

 

SPI

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

I2S

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

 

CAN 2.0B

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

 

Ethernet

MAC

1

1

1

1

1

1

1

1

GPIO

51

51

51

51

51

51

80

80

EXMC

0

0

0

0

0

0

1

1

EXTI

16

16

16

16

16

16

16

16

ADC

Units

2

2

2

2

2

2

2

2

 

Channels

16

16

16

16

16

16

16

16

DAC

2

2

2

2

2

2

2

2

 

 

Part Number

GD32F107xx

 

VD

VE

VF

VG

ZC

ZD

ZE

ZF

ZG

Flash (KB)

384

512

768

1024

256

384

512

768

1024

SRAM (KB)

96

96

96

96

96

96

96

96

96

Timers

GPTM(16

bit)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

 

Advanced

TM(16 bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

1

1

1

1

1

 

Basic TM(16

bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

U(S)ART

5

5

5

5

5

5

5

5

5

 

I2C

2

2

2

2

2

2

2

2

2

 

SPI

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

 

I2S

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

 

CAN 2.0B

2

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

1

 

Ethernet

MAC

1

1

1

1

1

1

1

1

1

GPIO

80

80

80

80

112

112

112

112

112

EXMC

1

1

1

1

1

1

1

1

1

EXTI

16

16

16

16

16

16

16

16

16

ADC

Units

2

2

2

2

2

2

2

2

2

 

Channels

16

16

16

16

16

16

16

16

16

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP100

LQFP144

 

Memory map

Table 2-3. GD32F107xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

External

device

 

 

 

 

AHB

 

0xA000 0000 - 0xA000 0FFF

 

EXMC - SWREG

 

 

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC -

NOR/PSRAM/SRA M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

Reserved

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

Reserved

 

 

0x4002 6000 - 0x4002 63FF

Reserved

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

Reserved

 

 

0x4002 3C00 - 0x4002 3FFF

Reserved

 

 

0x4002 3800 - 0x4002 3BFF

Reserved

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2C00 - 0x4002 2FFF

Reserved

 

 

0x4002 2800 - 0x4002 2BFF

Reserved

 

 

0x4002 2400 - 0x4002 27FF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1C00 - 0x4002 1FFF

Reserved

 

 

0x4002 1800 - 0x4002 1BFF

Reserved

 

 

0x4002 1400 - 0x4002 17FF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0C00 - 0x4002 0FFF

Reserved

 

 

0x4002 0800 - 0x4002 0BFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA1

 

 

0x4002 0000 - 0x4002 03FF

DMA0

 

 

0x4001 8400 - 0x4001 FFFF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 8000 - 0x4001 83FF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 7C00 - 0x4001 7FFF

Reserved

 

 

0x4001 7800 - 0x4001 7BFF

Reserved

 

 

0x4001 7400 - 0x4001 77FF

Reserved

 

 

0x4001 7000 - 0x4001 73FF

Reserved

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5C00 - 0x4001 67FF

Reserved

 

 

0x4001 5800 - 0x4001 5BFF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

Reserved

 

 

0x4001 5000 - 0x4001 53FF

Reserved

 

 

0x4001 4C00 - 0x4001 4FFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

Reserved

 

 

0x4001 4400 - 0x4001 47FF

Reserved

 

 

0x4001 4000 - 0x4001 43FF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

Reserved

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

 

0x4000 6000 - 0x4000 63FF

Shared CAN SRAM

512 bytes

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

Reserved

 

 

0x4000 1C00 - 0x4000 1FFF

Reserved

 

 

0x4000 1800 - 0x4000 1BFF

Reserved

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

 

 

SRAM

 

 

 

 

 

AHB

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2006 0000 - 0x2006 FFFF

Reserved

 

 

0x2003 0000 - 0x2005 FFFF

Reserved

 

 

0x2002 0000 - 0x2002 FFFF

Reserved

 

 

0x2001 C000 - 0x2001 FFFF

Reserved

 

 

0x2001 8000 - 0x2001 BFFF

Reserved

 

 

0x2000 5000 - 0x2001 7FFF

 

SRAM

 

 

0x2000 0000 - 0x2000 4FFF

 

 

Code

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF F000 - 0x1FFF F7FF

Boot loader

 

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

 

0x1FFF C010 - 0x1FFF EFFF

 

0x1FFF C000 - 0x1FFF C00F

0x1FFF B000 - 0x1FFF BFFF

0x1FFF 7A10 - 0x1FFF AFFF

Reserved

0x1FFF 7800 - 0x1FFF 7A0F

Reserved

0x1FFF 0000 - 0x1FFF 77FF

Reserved

0x1FFE C010 - 0x1FFE FFFF

Reserved

0x1FFE C000 - 0x1FFE C00F

Reserved

0x1001 0000 - 0x1FFE BFFF

Reserved

0x1000 0000 - 0x1000 FFFF

Reserved

0x083C 0000 - 0x0FFF FFFF

Reserved

0x0830 0000 - 0x083B FFFF

Reserved

0x0810 0000 - 0x082F FFFF

 

Main Flash

0x0802 0000 - 0x080F FFFF

0x0800 0000 - 0x0801 FFFF

0x0030 0000 - 0x07FF FFFF

Reserved

0x0010 0000 - 0x002F FFFF

 

Aliased to Main Flash or Boot loader

0x0002 0000 - 0x000F FFFF

0x0000 0000 - 0x0001 FFFF

 

GD32F107Zx LQFP144 pin definitions

Table 2-4. GD32F107Zx LQFP144 pin definitions

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4 Alternate:TRACED1, EXMC_A20

 

PE5

 

4

 

I/O

 

5VT

Default: PE5 Alternate:TRACED2, EXMC_A21

 

PE6

 

5

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3, EXMC_A22

VBAT

6

P

 

Default: VBAT

PC13-

TAMPER- RTC

 

7

 

I/O

 

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

 

8

 

I/O

 

Default: PC14 Alternate: OSC32IN

PC15- OSC32OUT

 

9

 

I/O

 

Default: PC15 Alternate: OSC32OUT

 

PF0

 

10

 

I/O

 

5VT

Default: PF0 Alternate: EXMC_A0

 

PF1

 

11

 

I/O

 

5VT

Default: PF1

Alternate: EXMC_A1

 

PF2

 

12

 

I/O

 

5VT

Default: PF2

Alternate: EXMC_A2

 

PF3

 

13

 

I/O

 

5VT

Default: PF3

Alternate: EXMC_A3

 

PF4

 

14

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4

 

PF5

 

15

 

I/O

 

5VT

Default: PF5 Alternate: EXMC_A5

VSS_5

16

P

 

Default: VSS_5

VDD_5

17

P

 

Default: VDD_5

PF6

18

I/O

 

Default: PF6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_NIORD

PF7

19

I/O

 

Default: PF7

 

 

 

 

Alternate: EXMC_NREG

PF8

20

I/O

 

Default: PF8

 

 

 

 

Alternate: EXMC_NIOWR

PF9

21

I/O

 

Default: PF9

 

 

 

 

Alternate: EXMC_CD

PF10

22

I/O

 

Default: PF10

 

 

 

 

Alternate: EXMC_INTR

OSCIN

23

I

 

Default: OSCIN

 

 

 

 

Remap: PD0

OSCOUT

24

O

 

Default: OSCOUT

 

 

 

 

Remap: PD1

NRST

25

I/O

 

Default: NRST

PC0

26

I/O

 

Default: PC0

 

 

 

 

Alternate: ADC01_IN10

 

 

 

 

Default: PC1

PC1

27

I/O

 

Alternate: ADC01_IN11, ETH_MII_MDC,

 

 

 

 

ETH_RMII_MDC

PC2

28

I/O

 

Default: PC2

 

 

 

 

Alternate: ADC01_IN12, ETH_MII_TXD2

PC3

29

I/O

 

Default: PC3

 

 

 

 

Alternate: ADC01_IN13, ETH_MII_TX_CLK

VSSA

30

P

 

Default: VSSA

VREF-

31

P

 

Default: VREF-

VREF+

32

P

 

Default: VREF+

VDDA

33

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

34

I/O

 

Alternate: WKUP, USART1_CTS, ADC01_IN0,

TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,

 

 

 

 

TIMER7_ETI, ETH_MII_CRS

 

 

 

 

Default: PA1

PA1

35

I/O

 

Alternate: USART1_RTS, ADC01_IN1,

TIMER1_CH1, TIMER4_CH1,

 

 

 

 

ETH_MII_RX_CLK, ETH_RMII_REF_CLK

 

 

 

 

Default: PA2

PA2

36

I/O

 

Alternate: USART1_TX, ADC01_IN2,

TIMER1_CH2, TIMER4_CH2, ETH_MII_MDIO,

 

 

 

 

ETH_RMII_MDIO

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Default: PA3

PA3

37

I/O

 

Alternate: USART1_RX, ADC01_IN3,

 

 

 

 

TIMER1_CH3, TIMER4_CH3, ETH_MII_COL

VSS_4

38

P

 

Default: VSS_4

VDD_4

39

P

 

Default: VDD_4

 

 

 

 

Default: PA4

PA4

40

I/O

 

Alternate: SPI0_NSS, USART1_CK,

ADC01_IN4, DAC_OUT0

 

 

 

 

Remap:SPI2_NSS, I2S2_WS

PA5

41

I/O

 

Default: PA5

 

 

 

 

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

 

 

 

 

Default: PA6

PA6

42

I/O

 

Alternate: SPI0_MISO, ADC01_IN6,

TIMER2_CH0, TIMER7_BKIN

 

 

 

 

Remap: TIMER0_BKIN

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, ADC01_IN7,

PA7

43

I/O

 

TIMER2_CH1, TIMER7_CH0_ON,

 

 

 

 

ETH_MII_RX_DV, ETH_RMII_CRS_DV

 

 

 

 

Remap: TIMER0_CH0_ON

 

 

 

 

Default: PC4

PC4

44

I/O

 

Alternate: ADC01_IN14, ETH_MII_RXD0,

 

 

 

 

ETH_RMII_RXD0

 

 

 

 

Default: PC5

PC5

45

I/O

 

Alternate: ADC01_IN15, ETH_MII_RXD1,

 

 

 

 

ETH_RMII_RXD1

 

 

 

 

Default: PB0

PB0

46

I/O

 

Alternate: ADC01_IN8, TIMER2_CH2,

TIMER7_CH1_ON, ETH_MII_RXD2

 

 

 

 

Remap: TIMER0_CH1_ON

 

 

 

 

Default: PB1

PB1

47

I/O

 

Alternate: ADC01_IN9, TIMER2_CH3,

TIMER7_CH2_ON, ETH_MII_RXD3

 

 

 

 

Remap: TIMER0_CH2_ON

PB2

48

I/O

5VT

Default: PB2, BOOT1

PF11

49

I/O

5VT

Default: PF11

 

 

 

 

Alternate: EXMC_NIOS16

PF12

50

I/O

5VT

Default: PF12

 

 

 

 

Alternate: EXMC_A6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VSS_6

51

P

 

Default: VSS_6

VDD_6

52

P

 

Default: VDD_6

 

PF13

 

53

 

I/O

 

5VT

Default: PF13 Alternate: EXMC_A7

 

PF14

 

54

 

I/O

 

5VT

Default: PF14

Alternate: EXMC_A8

 

PF15

 

55

 

I/O

 

5VT

Default: PF15 Alternate: EXMC_A9

 

PG0

 

56

 

I/O

 

5VT

Default: PG0 Alternate: EXMC_A10

 

PG1

 

57

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11

 

PE7

 

58

 

I/O

 

5VT

Default: PE7 Alternate: EXMC_D4 Remap: TIMER0_ETI

 

PE8

 

59

 

I/O

 

5VT

Default: PE8 Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

 

PE9

 

60

 

I/O

 

5VT

Default: PE9 Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

61

P

 

Default: VSS_7

VDD_7

62

P

 

Default: VDD_7

 

PE10

 

63

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

PE11

 

64

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8 Remap: TIMER0_CH1

 

PE12

 

65

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

 

PE13

 

66

 

I/O

 

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2

 

PE14

 

67

 

I/O

 

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3

PE15

68

I/O

5VT

Default: PE15 

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_D12

Remap: TIMER0_BKIN

 

 

PB10

 

 

69

 

 

I/O

 

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX, ETH_MII_RX_ER

Remap: TIMER1_CH2

 

 

PB11

 

 

70

 

 

I/O

 

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX, ETH_MII_TX_EN, ETH_RMII_TX_EN

Remap: TIMER1_CH3

VSS_1

71

P

 

Default: VSS_1

VDD_1

72

P

 

Default: VDD_1

 

 

PB12

 

 

73

 

 

I/O

 

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, I2S1_WS, CAN1_RX, ETH_MII_TXD0, ETH_RMII_TXD0

 

 

PB13

 

 

74

 

 

I/O

 

 

5VT

Default: PB13

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX, ETH_MII_TXD1, ETH_RMII_TXD1

 

PB14

 

75

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON

 

PB15

 

76

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD

 

 

PD8

 

 

77

 

 

I/O

 

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX, ETH_MII_RX_DV,

ETH_RMII_CRS_DV

 

 

PD9

 

 

78

 

 

I/O

 

 

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX, ETH_MII_RXD0,

ETH_RMII_RXD0

 

 

PD10

 

 

79

 

 

I/O

 

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, ETH_MII_RXD1,

ETH_RMII_RXD1

PD11

80

I/O

5VT

Default: PD11

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_A16

Remap: USART2_CTS, ETH_MII_RXD2

 

 

PD12

 

 

81

 

 

I/O

 

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS,

ETH_MII_RXD3

 

PD13

 

82

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18 Remap: TIMER3_CH1

VSS_8

83

P

 

Default: VSS_8

VDD_8

84

P

 

Default: VDD_8

 

PD14

 

85

 

I/O

 

5VT

Default: PD14 Alternate: EXMC_D0

Remap: TIMER3_CH2

 

PD15

 

86

 

I/O

 

5VT

Default: PD15 Alternate: EXMC_D1 Remap: TIMER3_CH3

 

PG2

 

87

 

I/O

 

5VT

Default: PG2 Alternate: EXMC_A12

 

PG3

 

88

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13

 

PG4

 

89

 

I/O

 

5VT

Default: PG4

Alternate: EXMC_A14

 

PG5

 

90

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15

 

PG6

 

91

 

I/O

 

5VT

Default: PG6

Alternate: EXMC_INT1

 

PG7

 

92

 

I/O

 

5VT

Default: PG7 Alternate: EXMC_INT2

PG8

93

I/O

5VT

Default: PG8

VSS_9

94

P

 

Default: VSS_9

VDD_9

95

P

 

Default: VDD_9

 

PC6

 

96

 

I/O

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

 

PC7

 

97

 

I/O

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

PC8

98

I/O

5VT

Default: PC8

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: TIMER7_CH2

Remap: TIMER2_CH2

 

PC9

 

99

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

 

PA8

 

100

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF

 

PA9

 

101

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

 

PA10

 

102

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

 

PA11

 

103

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

 

PA12

 

104

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

 

PA13

 

105

 

I/O

 

5VT

Default: JTMS, SWDIO Remap: PA13

NC

106

 

 

-

VSS_2

107

P

 

Default: VSS_2

VDD_2

108

P

 

Default: VDD_2

 

PA14

 

109

 

I/O

 

5VT

Default: JTCK, SWCLK

Remap: PA14

 

 

PA15

 

 

110

 

 

I/O

 

 

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

111

 

I/O

 

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

 

PC11

 

112

 

I/O

 

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

 

PC12

 

113

 

I/O

 

5VT

Default: PC12 Alternate: UART4_TX

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

114

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2 Remap: CAN0_RX

 

PD1

 

115

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX

 

PD2

 

116

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

 

PD3

 

117

 

I/O

 

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS

 

PD4

 

118

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

119

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

VSS_10

120

 

 

Default: VSS_10

VDD_10

121

 

 

Default: VDD_10

 

PD6

 

122

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT Remap: USART1_RX

 

PD7

 

123

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

124

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2

 

PG10

 

125

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2

 

PG11

 

126

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1

 

PG12

 

127

 

I/O

 

5VT

Default: PG12 Alternate: EXMC_NE3

 

PG13

 

128

 

I/O

 

5VT

Default: PG13

Alternate: EXMC_A24

 

PG14

 

129

 

I/O

 

5VT

Default: PG14

Alternate: EXMC_A25

VSS_11

130

P

 

Default: VSS_11

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VDD_11

131

P

 

Default: VDD_11

PG15

132

I/O

5VT

Default: PG15

 

 

PB3

 

 

133

 

 

I/O

 

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1,

SPI0_SCK

 

PB4

 

134

 

I/O

 

5VT

Default: NJTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

 

PB5

 

 

135

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD, ETH_PPS_OUT

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

 

PB6

 

136

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX

 

 

PB7

 

 

137

 

 

I/O

 

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV

Remap: USART0_RX

BOOT0

138

I

 

Default: BOOT0

 

PB8

 

139

 

I/O

 

5VT

Default: PB8

Alternate: TIMER3_CH2, ETH_MII_TXD3 Remap: I2C0_SCL, CAN0_RX

 

PB9

 

140

 

I/O

 

5VT

Default: PB9

Alternate: TIMER3_CH3 Remap: I2C0_SDA, CAN0_TX

PE0

141

I/O

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0

PE1

142

I/O

5VT

Default: PE1

Alternate: EXMC_NBL1

VSS_3

143

P

 

Default: VSS_3

VDD_3

144

P

 

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
 

ARM® Cortex™-M3 core

The Cortex™-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex™-M3 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 1024 Kbytes of Flash memory
96 Kbytes of SRAM

The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash at most and 96 Kbytes of inner SRAM is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Table 2-3. GD32F107xx memory map shows the memory map of the GD32F107xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low- speed APB domain is 54 MHz. See Figure 2-5. GD32F107xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6), USBFS in device mode (PA9, PA11 and PA12). It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by

setting a bit in option bytes.


Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC engine
Up to 1 MSPS conversion rate
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to two 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general-purpose timers (TIMERx) and the advanced-control timers (TIMER0 and TIMER7) with internal connection. The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage

into a digital value.


Digital to analog converter (DAC)

Two 12-bit DAC converters of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The two 12-bit buffered DAC channels are used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.

DMA

7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S
Dedicated DMA controller with the Ethernet application

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

3.9.General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable

There are up to 112 general purpose I/O pins (GPIO) in GD32F107xx, named PA0 ~ PA15 and  PB0  ~ PB15,  PC0  ~  PC15,  PD0  ~ PD15,  PE0  ~  PE15,  PF0-PF15,  PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are

shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Up to two 16-bit advanced-control timer (TIMER0 & TIMER7), four 16-bit general-purpose timers (GPTM), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each GPTM and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced-control timer (TIMER0 & TIMER7) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead- time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for
Input capture
Output compare
PWM generation (edge- or center-aligned counting modes)
Single pulse mode output

If configured as a general-purpose 16-bit timer, it has the same functions as the TIMER x timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), known as TIMER1 ~ TIMER4 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The GPTM also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F107xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.

The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART4.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F107xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error.

Universal serial bus full-speed (USBFS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for USB CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Ethernet MAC interface

IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 17 with 25 MHz output and RMII up to 9 with 50 MHz output. The function of 32-bit CRC checking is also available.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and

CF card
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F107Zx), LQFP100 (GD32F107Vx), LQFP64 (GD32F107Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

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发布时间: : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用,如今,家用电器的智能化已成为一种常态,越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入,今天就来说说这个话题。 什么是智能浴室镜?智慧型浴室镜,顾名思义,就是卫浴镜子智能化升级,入门级产品基本具备了彩灯和镜面触摸功能,更高档次的产品安装有微波雷达传感器智能感应,当感应到有人接近到一定距离即可开启亮灯或者亮屏操作,也可三色无极调,智能除雾,语音交互,日程安排备忘,甚至在镜子上看电视,听音乐,气象预报,问题查询,智能控制,健康管理等。 智能化雷达感应浴室镜与普通镜的区别,为什么要选TA?,就功能而言,普通浴镜价格用它没有什么压力!而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言,普通浴镜功能单一,而微波雷达传感器智能浴室镜功能创新:镜子灯光色温和亮度可以自由调节,镜面还可以湿手触控,智能除雾,既环保又健康! 尽管智能浴镜比较新颖,但功能丰富,体验感更好,特别是入门级的智能浴镜,具有基础智能化功能,真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么? ①确定智能浴室镜的安装位置,因为是安装时在墙壁上打孔,一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时,根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后,在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度,一般智能浴镜的标准安装高度约85cm(从地砖到镜子底),具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍,可用酒精或30%清洁稀释液擦洗,平时可用干毛巾养护,注意多通风。
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发布时间: : 2022-02--07
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智能家居wifi通信模块起重机无线模块应用优势

发布时间: : 2022-08--11
智能家居wifi通信模块起重机无线模块应用优势,我们都知道安全性在起重机工作运行中是需要重点考虑的,物联网通信技术的发展,特别是无线模块的应用使得无线控制技术在起重机行业上发挥着重要作用,不仅提高了起重机运行时的安全性和便利性,还实现了起重机的复杂操作。下面,一起来看一下无线模块应用于起重机等大型设备上有哪些优势。 起重机的安全由驾驶员的操作、(电缆线、护套管、拖链)等原件因腐蚀而造成刚度不够等因素决定,为了确保起重机的安全性,采集起重机各个特殊部位的信号,是解决问题的关键。 起重机结构复杂,不容易布线,所以信号的无线连接是解决起重机问题的有效途径。由于通信技术发展相比几年前更加成熟,无线的通信产品无线模块实测可达到几百米米,要想达到更远的距离可选功率更大的模块来实现。 起重机工作运行中存在哪些问题,在工作的往返过程中,起重机电缆线会持续被弯折,因此这种情况会导致一个重要的维护问题,一般桥式起重机会使用柔性电线护套管或拖链来减小因弯折而施加在电缆线上的压力。还有的预先将电缆线缠绕几圈从而减少电缆弯折的幅度。以上的几个办法虽然能改善起重机工作运行中的问题,但是仍然存在风险,因此还是需要更换电缆线。 如何解决起重机的问题?在起重机等大型设备中,使用无线模块替代电缆线的功能,没有电缆线可以直接减少后续的成本维护。在仓库地面利用无线操控一台桥式起重机,起重机的位置通过激光位移传感器来获取,一个测量X轴方向,一个测量Y轴方向的位置。 每个反射板式激光位移传感器输出一个信号,并且该信号被连接到一个模拟量输入端。无线设备定时对模拟量输出信号进行采集,从而获取桥式起重机的位置。由于无线设备和2个传感器都安装在移动的起重机上,所以只有很少量的电缆线被用来连接I/O信号,不会出现弯折的现象。 采用无线模块的优势: 一、通过无线传送位置信息从而降低碰撞的风险,减少了因为更换受损部件而受损的费用。 二、使用无线模块就没有电缆线损坏的风险,维护成本将大大降低。 三、控制系统安装期间不用铺设大量的电缆线。 以上就是起重机大型设备上工作运行时会出现的一些问题,以及针对这些问题给出的解决方案,通过使用无线模块控制起重机,可以提高安全性以及减少资金费用。 智能家居wifi通信模块无线和有线哪个更好,智能家居的通信系统可以分为有线和无线通信两大类。经过观察我们发现国外大型智能家居企业一般选择有线通信,而我国的智能家居企业基本上选择无线通信技术。同样的行业,同样的需求,为什么会有不同的选择? 国内智能家居厂家为何偏爱无线通信技术? 物联网作为构建信息化社会的重要举措一直,得到了政策层面的支持,进一步加速了我国智能家居的发展。国内很多智能家居厂商根据使用中、开发商、销售商等多方需求,多数选择了无线通信技术作为智能家居的通信解决方案。 市面上常见的智能家居无线通信技术有:无线射频、ZigBee、WiFi、蓝牙、红外等,国内厂家选择无线技术的原因是相比有线通信方式,无线智能家居产品特点在于无需凿强布线,安装简单灵活,设备可自动组网,功耗低,拓展性强,维护成本低,方便后期维修。 国外智能家居企业为何钟爱于有线? 很早以前,国外智能家居以有线方式为研发基础,该行业出现CresNet、C-BUS、X-10控制总线路、PLCBUS、CEBus总线、485总线等现场总线通信协议,目前知名的就是欧洲总线技术,ABB、施耐德等品牌均采用此总线技术。 有线技术数据传输具有可靠性强、抗干扰性强、传输速率高、不受环境影响的优势,而功能稳定是总线技术的一大优点。然而,稳定的另一面代表着不太方便改造,有线通信技术的产品采用布线的方式,工期长,价格高,售后维护复杂。在房屋装修期间预先走线安装,若是线路损坏,家居设备控制有故障,维护成本就比较高。复杂的布线,问题超多的施工,拓展性差等问题导致有线智能家居的产品一般适用于前装市场。 智能家居通信技术有线和无线通信方式各有优点,随着物联网技术的不断发展,未来越来越多的智能家居产品将采用无线模块的无线通信方式进行通信,这和当下的绿色环保理念不谋而合。
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10
2022-08

低功耗无线射频模块发展趋势无线模块清洁维护保养

发布时间: : 2022-08--10
低功耗无线射频模块发展趋势无线模块清洁维护保养,物联网的发展势头非常迅猛,射频模块得到了企业的大力推广,并且广泛应用到安防监控、远程抄表、工业控制、无人机、车载等领域中。目前模块行业的真实需求,以及未来射频模块的发展趋势,业界知名的通信、物联、射频模块厂商发表了自己的看法。 据悉,预计全国无线通信数量会超过10亿,随着新兴领域的快速发展,如:移动支付、电力、安防监控、车载等领域,针对这些领域投入资源会比较多,并将重点放在低功耗无线射频模块上,并针对重点客户提供定制化解决方案。 针对未来低功耗无线射频模块的技术发展趋势,我们认为模块会朝着智能化、低功耗、小体积、的方向发展,比如:在车载娱乐产品中,如后视镜、车机等应用均要求带操作系统,后还有越来越多的POS机因为要求支持指纹、手写签字等多种支付方式,也需要操作系统。因此,很多方案商直接采用手机或平板方案来设计产品,这对低功耗无线射频模块厂商提出了新的要求。 随着物联网产品形态不断增多,一方面模块的价格会持续走低,另一方面,互联网模块还会想着多样化的方向发展,以满足越来越多不同类型设备的功能需求。在不久的将来,我们甚至还会看到一些面向相对的利基市场的物联模块的出现。就像任何产品一样,模块也会有个性化、小众化的型号出现,而且模块不像芯片,前者实现个性化的成本要低很多。 对于射频元器件厂家来说,现在是竞争比较激烈的,低功耗无线射频模块元器件已经成为国内手机生产厂商特别关注的物料了,随着技术的提升,进入5G时代后,手机的频段需求不断增加,尤其是射频放大器和射频开关。 机遇往往伴随着挑战而出现,频谱在5G-LTE时代是稀缺资源,各个国家的频段间隔比较密集,这样就会对滤波器的性能提出更高的要求,高性能的滤波器就会成为市场的必需的产品之一。随着射频技术发展到5G+的时候,也就是出现更多频段的载波聚合时,手机对高性能的滤波器依赖会更明显。 物联网的持续发展,带来的不只是新的技术、新的产品,由于产品形态化的增多,终端产品厂商对射频模块的要求也会越来越高,低功耗、小体积、智能化将是射频模块的发展趋势。 无线模块清洁、维护保养的技巧方法,无线模块通过无线方式传输数据,比有线通信方式更方便维护。模块在生产过程中会经过多个工序,模块的屏蔽罩会有灰尘杂物,以及焊接部位会有松香等残留物,那么,无线模块如何清洁才能保持外观的整洁美观,如何维护保养才能延长模块的使用寿命,从而能够保持良好的工作状态? 无线模块的屏蔽罩沾了灰尘,或者模块的PCB板上焊接了天线SMA头之后,表面残留一些助焊剂、松香得物质,通过使用洗板水(电路板清洁剂的俗称)来清洁,可以使模块变得干净。 1.准备好专用的口罩、橡胶手套、洗板水、棉签等物品,带上口罩和橡胶手套做好防护措施(洗板水容易蒸发有刺激性气味,且对直接接触的皮肤有腐蚀性,因此要做好防护措施)。 2.使用棉签或纸巾挤压装着洗板水的瓶子,将蘸了适量洗板水的棉签在焊接处擦拭松香等残留物,屏蔽罩的清洁可用蘸了适量洗板水的纸巾轻轻擦拭。 3.将清洁干净的无线模块放到指定的盒子中,然后放到吸塑盒摆放整齐储存好。   无线模块维护保养技巧: 为了保持模块的良好工作状态,应该避免在高温、湿润、强电磁场的环境中使用。 不要使模块接连不断地处于发射的工作状态,可能会烧坏发射机,不要带点插、拔串口,容易烧坏通讯接口。 应选用直流稳压电源、有防雷、过流、过压的作用。 以上就是对无线模块清洁、维护保养的技巧,在使用中要特别注意以上提到的几点,这样才能保证模块处于良好的工作状态,延长模块的使用寿命。
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09
2022-08

乐鑫WiFi模块无线高性能指标使安防产品环保节能

发布时间: : 2022-08--09
乐鑫WiFi模块无线高性能指标使安防产品环保节能,安防产品市场竞争激烈,随着人们生活水平的不断提高,对安防产品的要求也不断提高,环保、节能成为人们关注的重点。乐鑫WiFi模块应用于门磁、监控等安防产品,使得安防产品更加节能环保,助力安防企业朝着环保节能之路前进。 随着安防行业快速发展,以及人们对安全需求的重视,节能型产品的需要日益显现出来。纵观安防行业的产品同质化日趋严重,已经无法满足人们对节能环保的需求。安防企业如何在竞争中脱颖而出,获得更大的市场份额已经成为各大安防公司的一大难题,安防产品的节能环保无疑成为当下的亮点。 安防市场的不断升温,以及使用安防产品的领域不断扩大。节能的安防产品将成为安防行业发展的趋势,节能安防产品更加符合市场需求。乐鑫WiFi模块无线作为安防产品的重要部分组成,具有低功耗、小体积、收发一体、使用寿命长的优势特点,这些优势特点能够使安防产品更加环保节能,未来几年,乐鑫WiFi模块将在安防行业各类产品中被广泛应用。 节能环保将成为安防市场发展的趋势,安防产品节能环保的特点并不会导致成本的增加,但是可能会使得安防行业发生一次的变革,从单纯的防盗报警、门禁对讲各自独立的应用,进入到安防产品信息化、多元化的发展,从而使安防市场的商机更加大。 无线收发模块主要关注哪些性能指标,市面上的WiFi模块无线种类繁多,质量良莠不齐,在千千万万的模块中,选择合适的模块并不是一件容易的事。其实,购买乐鑫WiFi模块的时候主要关注以下几个参数性能指标,大家不妨参考一下,有助于选购够合适的无线收发模块。选购时,主要考虑无线收发模块性能指标有:接收灵敏度、频率、功率、功耗等。   一、接收灵敏度 随着物联网的不断发展,无线WiFi模块的应用越来越广泛,业界对模块的灵敏度要求越来越高,无线前端收发模块高达-121dBm,符合使用标准。此外,需要注意的是接收灵敏度和传输距离相关联,灵敏度越高,传输距离越远,超高的接收灵敏度可用于要求远距离传输和可靠性要求极高的场合。   二、频率 在不同国家不同项目中,使用的频率可能不一样,需根据项目实际情况,匹配合适频率的无线WiFi模块。一般前端无线收发模块的频率范围可选2.4、5.8GHz,也可定制频段范围内的频率。   三、模块的功率 模块的输出功率对传输距离的影响比较大,功率越大,通信距离越远。在这个行业有点经验的人应该知道,模块的距离越远,功率越大,体积也就越大。因此,不能只考虑功率和距离,要考虑模块的尺寸是否能够嵌入到设备当中。   四、模块的功耗 无线WiFi模块的功耗包括:接收电流、发射电流、休眠电流。低功耗和远距离一般不可兼得,然而这两年迅速发展起来的新型模块,可以使低功耗下实现超远距离传输。此外,低功耗的模块适合用于需要电池供电的项目方案中。   无线WiFi模块主要关注接收灵敏度、频率、功率、功耗、工作电压、工作温度等性能指标。当然,还应该考虑尺寸、距离、成本等因素,为了选购到合适的模块,避免后期因为自身原因选择不当导致退货问题。
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