这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F107VGT6-GD32 ARM Cortex-M3 Microcontroller

兆易创新GD32F107VGT6-GD32 ARM Cortex-M3 Microcontroller GigaDevice Semiconductor Inc. GD32F107xx ARM® Cortex™-M3 32-bit MCU Datasheet General description The GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F107xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS and an Ethernet MAC. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F107xx devices suitable for a wide range of interconnection applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.   Device information Table 2-1. GD32F107xx devices features and peripheral list   Part Number GD32F107xx   RB RC RD RE RF RG VB VC Flash (KB) 128 256 384 512 768 1024 128 256 SRAM (KB) 96 96 96 96 96 96 96 96 Timers GPTM(16 bit) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4) 4 (1-4)   Advanced TM(16 bit) 1 (0) 1 (0) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 1 (0) 1 (0)   SysTick 1 1 1 1 1 1 1 1   Basic TM(16 bit) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6)   Watchdog 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 Connectivity U(S)ART 5 5 5 5 5 5 5 5   I2C 1 (0) 1 (0) 2 (0-1) 2 (0-1) 2 (0-1) 2 (0-1) 1 (0) 1 (0)   SPI 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2)   I2S 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2) 2 (1-2)   CAN 2.0B 2 2 2 2 2 2 2 2   USBFS 1 1 1 1 1 1 1 1   Ethernet MAC 1 1 1 1 1 1 1 1 GPIO 51 51 51 51 51 51 80 80 EXMC 0 0 0 0 0 0 1 1
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F107VGT6-GD32 ARM Cortex-M3 Microcontroller

GigaDevice Semiconductor Inc.
GD32F107xx
ARM® Cortex™-M3 32-bit MCU
Datasheet

General description

The GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F107xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS and an Ethernet MAC.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F107xx devices suitable for a wide range of interconnection applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.
 

Device information

Table 2-1. GD32F107xx devices features and peripheral list

 

Part Number

GD32F107xx

 

RB

RC

RD

RE

RF

RG

VB

VC

Flash (KB)

128

256

384

512

768

1024

128

256

SRAM (KB)

96

96

96

96

96

96

96

96

Timers

GPTM(16

bit)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

 

Advanced

TM(16 bit)

1

(0)

1

(0)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

1

(0)

1

(0)

 

SysTick

1

1

1

1

1

1

1

1

 

Basic TM(16

bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

Watchdog

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

Connectivity

U(S)ART

5

5

5

5

5

5

5

5

 

I2C

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

1

(0)

1

(0)

 

SPI

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

I2S

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

 

CAN 2.0B

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

 

Ethernet

MAC

1

1

1

1

1

1

1

1

GPIO

51

51

51

51

51

51

80

80

EXMC

0

0

0

0

0

0

1

1

EXTI

16

16

16

16

16

16

16

16

ADC

Units

2

2

2

2

2

2

2

2

 

Channels

16

16

16

16

16

16

16

16

DAC

2

2

2

2

2

2

2

2

 

 

Part Number

GD32F107xx

 

VD

VE

VF

VG

ZC

ZD

ZE

ZF

ZG

Flash (KB)

384

512

768

1024

256

384

512

768

1024

SRAM (KB)

96

96

96

96

96

96

96

96

96

Timers

GPTM(16

bit)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

4

(1-4)

 

Advanced

TM(16 bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

1

1

1

1

1

 

Basic TM(16

bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

U(S)ART

5

5

5

5

5

5

5

5

5

 

I2C

2

2

2

2

2

2

2

2

2

 

SPI

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

 

I2S

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

2

(1-2)

 

CAN 2.0B

2

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

1

 

Ethernet

MAC

1

1

1

1

1

1

1

1

1

GPIO

80

80

80

80

112

112

112

112

112

EXMC

1

1

1

1

1

1

1

1

1

EXTI

16

16

16

16

16

16

16

16

16

ADC

Units

2

2

2

2

2

2

2

2

2

 

Channels

16

16

16

16

16

16

16

16

16

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP100

LQFP144

 

Memory map

Table 2-3. GD32F107xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

External

device

 

 

 

 

AHB

 

0xA000 0000 - 0xA000 0FFF

 

EXMC - SWREG

 

 

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC -

NOR/PSRAM/SRA M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

Reserved

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

Reserved

 

 

0x4002 6000 - 0x4002 63FF

Reserved

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

Reserved

 

 

0x4002 3C00 - 0x4002 3FFF

Reserved

 

 

0x4002 3800 - 0x4002 3BFF

Reserved

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2C00 - 0x4002 2FFF

Reserved

 

 

0x4002 2800 - 0x4002 2BFF

Reserved

 

 

0x4002 2400 - 0x4002 27FF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1C00 - 0x4002 1FFF

Reserved

 

 

0x4002 1800 - 0x4002 1BFF

Reserved

 

 

0x4002 1400 - 0x4002 17FF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0C00 - 0x4002 0FFF

Reserved

 

 

0x4002 0800 - 0x4002 0BFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA1

 

 

0x4002 0000 - 0x4002 03FF

DMA0

 

 

0x4001 8400 - 0x4001 FFFF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 8000 - 0x4001 83FF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 7C00 - 0x4001 7FFF

Reserved

 

 

0x4001 7800 - 0x4001 7BFF

Reserved

 

 

0x4001 7400 - 0x4001 77FF

Reserved

 

 

0x4001 7000 - 0x4001 73FF

Reserved

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5C00 - 0x4001 67FF

Reserved

 

 

0x4001 5800 - 0x4001 5BFF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

Reserved

 

 

0x4001 5000 - 0x4001 53FF

Reserved

 

 

0x4001 4C00 - 0x4001 4FFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

Reserved

 

 

0x4001 4400 - 0x4001 47FF

Reserved

 

 

0x4001 4000 - 0x4001 43FF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

Reserved

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

 

0x4000 6000 - 0x4000 63FF

Shared CAN SRAM

512 bytes

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

Reserved

 

 

0x4000 1C00 - 0x4000 1FFF

Reserved

 

 

0x4000 1800 - 0x4000 1BFF

Reserved

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

 

 

SRAM

 

 

 

 

 

AHB

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2006 0000 - 0x2006 FFFF

Reserved

 

 

0x2003 0000 - 0x2005 FFFF

Reserved

 

 

0x2002 0000 - 0x2002 FFFF

Reserved

 

 

0x2001 C000 - 0x2001 FFFF

Reserved

 

 

0x2001 8000 - 0x2001 BFFF

Reserved

 

 

0x2000 5000 - 0x2001 7FFF

 

SRAM

 

 

0x2000 0000 - 0x2000 4FFF

 

 

Code

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF F000 - 0x1FFF F7FF

Boot loader

 

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

 

0x1FFF C010 - 0x1FFF EFFF

 

0x1FFF C000 - 0x1FFF C00F

0x1FFF B000 - 0x1FFF BFFF

0x1FFF 7A10 - 0x1FFF AFFF

Reserved

0x1FFF 7800 - 0x1FFF 7A0F

Reserved

0x1FFF 0000 - 0x1FFF 77FF

Reserved

0x1FFE C010 - 0x1FFE FFFF

Reserved

0x1FFE C000 - 0x1FFE C00F

Reserved

0x1001 0000 - 0x1FFE BFFF

Reserved

0x1000 0000 - 0x1000 FFFF

Reserved

0x083C 0000 - 0x0FFF FFFF

Reserved

0x0830 0000 - 0x083B FFFF

Reserved

0x0810 0000 - 0x082F FFFF

 

Main Flash

0x0802 0000 - 0x080F FFFF

0x0800 0000 - 0x0801 FFFF

0x0030 0000 - 0x07FF FFFF

Reserved

0x0010 0000 - 0x002F FFFF

 

Aliased to Main Flash or Boot loader

0x0002 0000 - 0x000F FFFF

0x0000 0000 - 0x0001 FFFF

 

GD32F107Zx LQFP144 pin definitions

Table 2-4. GD32F107Zx LQFP144 pin definitions

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4 Alternate:TRACED1, EXMC_A20

 

PE5

 

4

 

I/O

 

5VT

Default: PE5 Alternate:TRACED2, EXMC_A21

 

PE6

 

5

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3, EXMC_A22

VBAT

6

P

 

Default: VBAT

PC13-

TAMPER- RTC

 

7

 

I/O

 

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

 

8

 

I/O

 

Default: PC14 Alternate: OSC32IN

PC15- OSC32OUT

 

9

 

I/O

 

Default: PC15 Alternate: OSC32OUT

 

PF0

 

10

 

I/O

 

5VT

Default: PF0 Alternate: EXMC_A0

 

PF1

 

11

 

I/O

 

5VT

Default: PF1

Alternate: EXMC_A1

 

PF2

 

12

 

I/O

 

5VT

Default: PF2

Alternate: EXMC_A2

 

PF3

 

13

 

I/O

 

5VT

Default: PF3

Alternate: EXMC_A3

 

PF4

 

14

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4

 

PF5

 

15

 

I/O

 

5VT

Default: PF5 Alternate: EXMC_A5

VSS_5

16

P

 

Default: VSS_5

VDD_5

17

P

 

Default: VDD_5

PF6

18

I/O

 

Default: PF6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_NIORD

PF7

19

I/O

 

Default: PF7

 

 

 

 

Alternate: EXMC_NREG

PF8

20

I/O

 

Default: PF8

 

 

 

 

Alternate: EXMC_NIOWR

PF9

21

I/O

 

Default: PF9

 

 

 

 

Alternate: EXMC_CD

PF10

22

I/O

 

Default: PF10

 

 

 

 

Alternate: EXMC_INTR

OSCIN

23

I

 

Default: OSCIN

 

 

 

 

Remap: PD0

OSCOUT

24

O

 

Default: OSCOUT

 

 

 

 

Remap: PD1

NRST

25

I/O

 

Default: NRST

PC0

26

I/O

 

Default: PC0

 

 

 

 

Alternate: ADC01_IN10

 

 

 

 

Default: PC1

PC1

27

I/O

 

Alternate: ADC01_IN11, ETH_MII_MDC,

 

 

 

 

ETH_RMII_MDC

PC2

28

I/O

 

Default: PC2

 

 

 

 

Alternate: ADC01_IN12, ETH_MII_TXD2

PC3

29

I/O

 

Default: PC3

 

 

 

 

Alternate: ADC01_IN13, ETH_MII_TX_CLK

VSSA

30

P

 

Default: VSSA

VREF-

31

P

 

Default: VREF-

VREF+

32

P

 

Default: VREF+

VDDA

33

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

34

I/O

 

Alternate: WKUP, USART1_CTS, ADC01_IN0,

TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,

 

 

 

 

TIMER7_ETI, ETH_MII_CRS

 

 

 

 

Default: PA1

PA1

35

I/O

 

Alternate: USART1_RTS, ADC01_IN1,

TIMER1_CH1, TIMER4_CH1,

 

 

 

 

ETH_MII_RX_CLK, ETH_RMII_REF_CLK

 

 

 

 

Default: PA2

PA2

36

I/O

 

Alternate: USART1_TX, ADC01_IN2,

TIMER1_CH2, TIMER4_CH2, ETH_MII_MDIO,

 

 

 

 

ETH_RMII_MDIO

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Default: PA3

PA3

37

I/O

 

Alternate: USART1_RX, ADC01_IN3,

 

 

 

 

TIMER1_CH3, TIMER4_CH3, ETH_MII_COL

VSS_4

38

P

 

Default: VSS_4

VDD_4

39

P

 

Default: VDD_4

 

 

 

 

Default: PA4

PA4

40

I/O

 

Alternate: SPI0_NSS, USART1_CK,

ADC01_IN4, DAC_OUT0

 

 

 

 

Remap:SPI2_NSS, I2S2_WS

PA5

41

I/O

 

Default: PA5

 

 

 

 

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

 

 

 

 

Default: PA6

PA6

42

I/O

 

Alternate: SPI0_MISO, ADC01_IN6,

TIMER2_CH0, TIMER7_BKIN

 

 

 

 

Remap: TIMER0_BKIN

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, ADC01_IN7,

PA7

43

I/O

 

TIMER2_CH1, TIMER7_CH0_ON,

 

 

 

 

ETH_MII_RX_DV, ETH_RMII_CRS_DV

 

 

 

 

Remap: TIMER0_CH0_ON

 

 

 

 

Default: PC4

PC4

44

I/O

 

Alternate: ADC01_IN14, ETH_MII_RXD0,

 

 

 

 

ETH_RMII_RXD0

 

 

 

 

Default: PC5

PC5

45

I/O

 

Alternate: ADC01_IN15, ETH_MII_RXD1,

 

 

 

 

ETH_RMII_RXD1

 

 

 

 

Default: PB0

PB0

46

I/O

 

Alternate: ADC01_IN8, TIMER2_CH2,

TIMER7_CH1_ON, ETH_MII_RXD2

 

 

 

 

Remap: TIMER0_CH1_ON

 

 

 

 

Default: PB1

PB1

47

I/O

 

Alternate: ADC01_IN9, TIMER2_CH3,

TIMER7_CH2_ON, ETH_MII_RXD3

 

 

 

 

Remap: TIMER0_CH2_ON

PB2

48

I/O

5VT

Default: PB2, BOOT1

PF11

49

I/O

5VT

Default: PF11

 

 

 

 

Alternate: EXMC_NIOS16

PF12

50

I/O

5VT

Default: PF12

 

 

 

 

Alternate: EXMC_A6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VSS_6

51

P

 

Default: VSS_6

VDD_6

52

P

 

Default: VDD_6

 

PF13

 

53

 

I/O

 

5VT

Default: PF13 Alternate: EXMC_A7

 

PF14

 

54

 

I/O

 

5VT

Default: PF14

Alternate: EXMC_A8

 

PF15

 

55

 

I/O

 

5VT

Default: PF15 Alternate: EXMC_A9

 

PG0

 

56

 

I/O

 

5VT

Default: PG0 Alternate: EXMC_A10

 

PG1

 

57

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11

 

PE7

 

58

 

I/O

 

5VT

Default: PE7 Alternate: EXMC_D4 Remap: TIMER0_ETI

 

PE8

 

59

 

I/O

 

5VT

Default: PE8 Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

 

PE9

 

60

 

I/O

 

5VT

Default: PE9 Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

61

P

 

Default: VSS_7

VDD_7

62

P

 

Default: VDD_7

 

PE10

 

63

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

PE11

 

64

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8 Remap: TIMER0_CH1

 

PE12

 

65

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

 

PE13

 

66

 

I/O

 

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2

 

PE14

 

67

 

I/O

 

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3

PE15

68

I/O

5VT

Default: PE15 

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_D12

Remap: TIMER0_BKIN

 

 

PB10

 

 

69

 

 

I/O

 

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX, ETH_MII_RX_ER

Remap: TIMER1_CH2

 

 

PB11

 

 

70

 

 

I/O

 

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX, ETH_MII_TX_EN, ETH_RMII_TX_EN

Remap: TIMER1_CH3

VSS_1

71

P

 

Default: VSS_1

VDD_1

72

P

 

Default: VDD_1

 

 

PB12

 

 

73

 

 

I/O

 

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, I2S1_WS, CAN1_RX, ETH_MII_TXD0, ETH_RMII_TXD0

 

 

PB13

 

 

74

 

 

I/O

 

 

5VT

Default: PB13

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX, ETH_MII_TXD1, ETH_RMII_TXD1

 

PB14

 

75

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON

 

PB15

 

76

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD

 

 

PD8

 

 

77

 

 

I/O

 

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX, ETH_MII_RX_DV,

ETH_RMII_CRS_DV

 

 

PD9

 

 

78

 

 

I/O

 

 

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX, ETH_MII_RXD0,

ETH_RMII_RXD0

 

 

PD10

 

 

79

 

 

I/O

 

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, ETH_MII_RXD1,

ETH_RMII_RXD1

PD11

80

I/O

5VT

Default: PD11

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: EXMC_A16

Remap: USART2_CTS, ETH_MII_RXD2

 

 

PD12

 

 

81

 

 

I/O

 

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS,

ETH_MII_RXD3

 

PD13

 

82

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18 Remap: TIMER3_CH1

VSS_8

83

P

 

Default: VSS_8

VDD_8

84

P

 

Default: VDD_8

 

PD14

 

85

 

I/O

 

5VT

Default: PD14 Alternate: EXMC_D0

Remap: TIMER3_CH2

 

PD15

 

86

 

I/O

 

5VT

Default: PD15 Alternate: EXMC_D1 Remap: TIMER3_CH3

 

PG2

 

87

 

I/O

 

5VT

Default: PG2 Alternate: EXMC_A12

 

PG3

 

88

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13

 

PG4

 

89

 

I/O

 

5VT

Default: PG4

Alternate: EXMC_A14

 

PG5

 

90

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15

 

PG6

 

91

 

I/O

 

5VT

Default: PG6

Alternate: EXMC_INT1

 

PG7

 

92

 

I/O

 

5VT

Default: PG7 Alternate: EXMC_INT2

PG8

93

I/O

5VT

Default: PG8

VSS_9

94

P

 

Default: VSS_9

VDD_9

95

P

 

Default: VDD_9

 

PC6

 

96

 

I/O

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

 

PC7

 

97

 

I/O

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

PC8

98

I/O

5VT

Default: PC8

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: TIMER7_CH2

Remap: TIMER2_CH2

 

PC9

 

99

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

 

PA8

 

100

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF

 

PA9

 

101

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

 

PA10

 

102

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

 

PA11

 

103

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

 

PA12

 

104

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

 

PA13

 

105

 

I/O

 

5VT

Default: JTMS, SWDIO Remap: PA13

NC

106

 

 

-

VSS_2

107

P

 

Default: VSS_2

VDD_2

108

P

 

Default: VDD_2

 

PA14

 

109

 

I/O

 

5VT

Default: JTCK, SWCLK

Remap: PA14

 

 

PA15

 

 

110

 

 

I/O

 

 

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

111

 

I/O

 

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

 

PC11

 

112

 

I/O

 

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

 

PC12

 

113

 

I/O

 

5VT

Default: PC12 Alternate: UART4_TX

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

114

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2 Remap: CAN0_RX

 

PD1

 

115

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX

 

PD2

 

116

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

 

PD3

 

117

 

I/O

 

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS

 

PD4

 

118

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

119

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

VSS_10

120

 

 

Default: VSS_10

VDD_10

121

 

 

Default: VDD_10

 

PD6

 

122

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT Remap: USART1_RX

 

PD7

 

123

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

124

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2

 

PG10

 

125

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2

 

PG11

 

126

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1

 

PG12

 

127

 

I/O

 

5VT

Default: PG12 Alternate: EXMC_NE3

 

PG13

 

128

 

I/O

 

5VT

Default: PG13

Alternate: EXMC_A24

 

PG14

 

129

 

I/O

 

5VT

Default: PG14

Alternate: EXMC_A25

VSS_11

130

P

 

Default: VSS_11

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VDD_11

131

P

 

Default: VDD_11

PG15

132

I/O

5VT

Default: PG15

 

 

PB3

 

 

133

 

 

I/O

 

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1,

SPI0_SCK

 

PB4

 

134

 

I/O

 

5VT

Default: NJTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

 

PB5

 

 

135

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD, ETH_PPS_OUT

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

 

PB6

 

136

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX

 

 

PB7

 

 

137

 

 

I/O

 

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV

Remap: USART0_RX

BOOT0

138

I

 

Default: BOOT0

 

PB8

 

139

 

I/O

 

5VT

Default: PB8

Alternate: TIMER3_CH2, ETH_MII_TXD3 Remap: I2C0_SCL, CAN0_RX

 

PB9

 

140

 

I/O

 

5VT

Default: PB9

Alternate: TIMER3_CH3 Remap: I2C0_SDA, CAN0_TX

PE0

141

I/O

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0

PE1

142

I/O

5VT

Default: PE1

Alternate: EXMC_NBL1

VSS_3

143

P

 

Default: VSS_3

VDD_3

144

P

 

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
 

ARM® Cortex™-M3 core

The Cortex™-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex™-M3 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 1024 Kbytes of Flash memory
96 Kbytes of SRAM

The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash at most and 96 Kbytes of inner SRAM is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Table 2-3. GD32F107xx memory map shows the memory map of the GD32F107xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low- speed APB domain is 54 MHz. See Figure 2-5. GD32F107xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6), USBFS in device mode (PA9, PA11 and PA12). It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by

setting a bit in option bytes.


Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC engine
Up to 1 MSPS conversion rate
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to two 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general-purpose timers (TIMERx) and the advanced-control timers (TIMER0 and TIMER7) with internal connection. The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage

into a digital value.


Digital to analog converter (DAC)

Two 12-bit DAC converters of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The two 12-bit buffered DAC channels are used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.

DMA

7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S
Dedicated DMA controller with the Ethernet application

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

3.9.General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable

There are up to 112 general purpose I/O pins (GPIO) in GD32F107xx, named PA0 ~ PA15 and  PB0  ~ PB15,  PC0  ~  PC15,  PD0  ~ PD15,  PE0  ~  PE15,  PF0-PF15,  PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are

shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Up to two 16-bit advanced-control timer (TIMER0 & TIMER7), four 16-bit general-purpose timers (GPTM), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each GPTM and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced-control timer (TIMER0 & TIMER7) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead- time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for
Input capture
Output compare
PWM generation (edge- or center-aligned counting modes)
Single pulse mode output

If configured as a general-purpose 16-bit timer, it has the same functions as the TIMER x timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), known as TIMER1 ~ TIMER4 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The GPTM also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F107xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.

The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART4.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F107xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error.

Universal serial bus full-speed (USBFS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for USB CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Ethernet MAC interface

IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 17 with 25 MHz output and RMII up to 9 with 50 MHz output. The function of 32-bit CRC checking is also available.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and

CF card
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F107Zx), LQFP100 (GD32F107Vx), LQFP64 (GD32F107Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

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发布时间: : 2022-01--14
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发布时间: : 2022-02--07
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无线通信芯片上海乐鑫官网代理商ESP32-C3照朋硬件设计

发布时间: : 2022-12--07
无线通信芯片上海乐鑫官网代理商ESP32-C3照朋硬件设计,本文介绍智能照明产品的主要组成及各种应用场景,并以LED智能灯为例说明智能照产品的主要硬件模块框架;然后介绍如何基于无线通信芯片上海乐鑫官网代理商ESP32-C3 芯片及模组设计一个智能照明产品实现调光、调色的控制以及无线通信功能,相关的设计方案也可以扩展应用于灯带、吸顶灯射灯等多种 LED智能照明产品中。 智能照明产品一般采用 LED 作为发光源,LED 是一种固态电光源,是一种半导体照明器件具有功耗低、寿命长,便于调节控制及无污染等特征,相比传统的照明产品,具有更高的光能转换效率。同时智能照明产品都具有无线连接功能,无线通信芯片上海乐鑫官网代理商支持通过 Wi-Fi Bluetooth LE 或 ZigBe连接到无线路由器或智能网关,然后连接互联网和云端服务器。用户不仅可以使用智能手机平板电脑、具有语音控制功能的智能音箱、智能控制面板等来调节 LED 智能灯的发光亮度和颜色;也可以设置多个定时开灯和关灯的时间;还可以把多个 LED 智能灯编组,同时控制-组 LED 智能灯的亮度和颜色。在 LED 智能灯中,可以预先设置多个灯光场景模式,用户自由切换多个灯光场景模式,满足家庭日常生活的需求,如打开影院模式,可以使整个环培灯光调暗;打开阅读模式,可以自动将灯光调节到不会伤害眼睛的柔和亮度;打开音乐模式不仅可以改变灯光的颜色,还可以实现灯光跟随音乐节奏的闪烁功能;在晚餐时,暖色灯光可以营造出温馨的用餐氛围;在入睡时,只需要打开睡眠模式即可关闭除夜灯外的所有灯光非常方便。 从以上说明中,我们了解到智能照明产品的主要特点是可以通过多种无线连接方式进行开关调光、调色等操作。下面以彩色 LED 智能灯为例,介绍智能照明产品的主要组成部分,以及控制功能的实现。 彩色 LED 智能灯的结构,主要包括连接灯座的 E27 标准灯头、塑胶包裹铝灯体电源及LED 驱动板、无线通信芯片上海乐鑫官网代理商Wi-Fi 模块、LED 灯珠及铝基板,以及高透光灯罩。与传统的 LED 球泡灯相比,彩色LED智能灯增加了一个 Wi-Fi/Bluetooth LE 模块,这个模块是如何实现彩色LED智能灯的无线控制的呢?下面将从功能实现方面进一步展开介绍。 彩色LED智能灯的功能单元框图,主要包括220VAC-DC 电源模块、LED驱动恒流源、3.3V输出辅助电源、PWM 控制及无线通信,以及多种颜色的 LED灯珠等。 LEDPWM的河光、诚色展,能明产品 (如彩色 LED 智能灯》发光亮度和颜色的化是通过对LED力湖皇原牌,“调色来实现的,其中调光方法主要分为横拟调光和数光,模拟调光是通过改进行图)打珠回路中电流大小来实现的:数字调光又称为PWM调是通过不同然宽的PWN信开启和关闭LED灯珠来改变正向电流的导通时间,从现调光的。这里先简单介绍使用 PWM 信号进行 PWM调光的方法。 使用可控制恒流源分别驱动LED灯珠时,可通过2路 PWM 信号的不同占空比来互补调节暖自(ww)和冷自CW)LED灯珠的动电流比例,实现色温的调节;可以通过3路PW信号的不同占空比控制对应不同颜色的亮度,彩色 LED 智能灯可以发出不同颜色 LED灯。 (1)220VAC-DC 电源模块。彩色 LED 智能灯的输入电源通常是高压交流电源,我国家用混合后的颜色,实现颜色的调节。准交流电源的电压为220V。220 VAC-DC 电源模块首先通过整流桥将交流电转换为直流并将电压降低到 18~40V,然后供给LED 驱动恒流源。因为PWM 控制及无线通信的工作压通常是 3.3 V,所以还有另一路直流降压的辅助电源,会把电压降低到 3.3 V。 (2)LED 驱动恒流源。为了确保多个 LED 灯珠发光的一致性,通常要把多个 LED 灯珠串在一起,并使用可控制恒流源来驱动。LED 灯珠的亮度可通过 PWM 信号控制恒流源来进行调节,LED 驱动恒流源1用于驱动冷白 (CW) 和暖白(WW)的 LED 灯珠,电源输出会比较大一些:LED驱动恒流源2用于驱动红色 (R)/绿色(G)(B)的LED灯珠主要用来调节颜色,电源输出功率相对小一些。 (3)LED 灯珠。在彩色 LED 智能灯中,通常都会包含暖白、冷白、红色、绿色、蓝色五种颜色的 LED 灯珠,其中暖白和冷白的 LED 灯珠数量会多一些,用于照明;红色、绿色和蓝的 LED 灯珠数量少一些,用于实现不同颜色的混色。 (4)PWM 控制及无线通信。在智能照明产品中,无线通信芯片上海乐鑫官网代理商为了实现PWM控制和无线通信功能,通常会选用具有无线通信功能的高集成度的系统级芯片(SoC)。系统级芯片支持多路 PWM信号输出,支持 Wi-Fi、Bluetooth LE 或 ZigBee 等一种或多种主流的无线通信功能,能够运行嵌入式RTOS,支持软件应用开发。如果使用支持 Wi-Fi功能的芯片,就可以通过 Wi-Fi 路由器接到互联网和云端服务器;如果使用支持 Buetooth LE 或 ZigBee 功能的芯片,则通常还需罗配置一个支持 Bluetooth LE或 ZigBee 的网关设备,通过网关设备转接到以太网或 Wi-Fi路器后,才能连接到互联网和云端服务器。 以上简要介绍了彩色 LED 智能灯的主要组成单元,以及调光、调色功能的实现,从中可以出,PWM控制及无线通信的使用是智能照明产品与普通照明产品的大区别。本文后续内将重点介绍如何基于无线通信芯片上海乐鑫官网代理商ESP32-C3芯片进行小便件系统设计,实现 PWM 调光、调色,以及线通信功能。这部分的功能实现也适用于射灯、吸项灯、灯具、灯带等多种智能照明产品。
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06
2022-12

无线通讯芯片wifimesh组网方案乐鑫代理商Mac系统安装ESP-IDF开发环境

发布时间: : 2022-12--06
无线通讯芯片wifimesh组网方案乐鑫代理商Mac系统安装ESP-IDF开发环境,在 Mac 系统下安装 ESPIDP 开发环境的流程和 Linux 系统一致,库代码下载和工具链安命令也完全相同,只是安装依赖软件包的命令略不相同。 1.安装依赖软件包 pip 作为Python 包管理工具,将用于后续 Python 软件包的安装。打开终端,输入以下命令安装pip: % sudo easy_install pip 安装包管理工具 HomeBrew 用于安装其他依赖软件,输入下面的命令可安装 HomeBrew: %    /bin/bash    -c    "$(curl-fsSI https://raw.githubusercontent.com/Homebrew/installlHEAD/install.sh) ” 输入以下命令可安装依赖软件包: % brew python3 install cmake ninja ccache dfu-util 2.下载ESP-IDF 仓库代码 与 Linux 系统中下载 ESP-IDF 仓库代码的方法相同 3.安装ESP-IDF开发工具链 与Linux 系统中安装 ESP-IDF 开发工具链的方法相同 VS Code代码编辑工具的安装 ESP-IDF SDK 默认不附带代码编辑工具(新的Windows 版安装工具可选择安装 ESP-IDFEclipse),读者可使用任何文本编辑工具进行代码的编辑,代码编辑完成后可在终端控制台使用命令进行代码的编译。 VS Code (VisualStudio Code) 是一个免费的代码编辑工具,具有丰富且易用的插件功能,支持代码跳转和高亮显示,支持 Git 版本管理和终端集成等。另外乐鑫科技也为 VS Code 开发了专用插件 EspressifIDF,方便工程配置和调试。 读者可以使用命令 code 在 VSCode 中快速打开当前文件夹,也可以使用命令 ctrl+~ 在 VSCode 中打开系统默认的终端控制台。 第三方开发环境简介 除了支持以C语言为主的官方开发环境 ESP-IDF,ESP32-C3 还支持其他主流开发语言和大量第三方开发环境,主要包括: (1)Arduino。是一个开源硬件和开源软件平台,支持包括 ESP32-C3 在内的大量微控制器Arduino 基于 C++ 语言的 API,由于使用简单和标准,在开发者社区广泛流行,也被称为Arduino 语言,被广泛应用在原型开发和教学领域。同时 Arduino 还提供一个可扩展软件包的IDE,可以一键完成代码编译和烧录工作。 (2)MicroPython。是可在嵌入式微控制器平台上运行的 Python3 语言解析器,通过简单的脚本语言即可直接调用ESP32-C3 的外设资源(如UART、SPI、I2C等)和通信功能(如 Wi-FiBluetooth LE),能够大大简化与硬件的交互过程。结合 Python 的大量数学运算库,用户可以在ESP32-C3 上轻松实现复杂的算法,加速人工智能相关应用的开发。借助脚本语言的特性用户不需要重复代码的编译和烧录过程,只需要修改运行脚本即可。 (3)NodeMCU。是一个针对 ESP 系列芯片开发的LUA 语言解析器,几乎支持 ESP 芯片的所有外设功能,相比MicroPython 也更加轻量。同样,NodeMCU 也有脚本语言,具有无须重复编译的优点。 除此以外,ESP32-C3 还支持 NuttX和Zephyr 操作系统。NuttX 是支持 POSIX 兼接口的实时操作系统,提高了应用软件的可移植性。Zephyr 是专为物联网场景开发的小型实时操作系统,包含了大量的物联网开发过程中需要的软件库,正逐渐发展为完整的软件生态系统。
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05
2022-12

ESP32-C3无线路由芯片乐鑫信息代理商ESP-IDF开发环境搭建

发布时间: : 2022-12--05
ESP32-C3无线路由芯片乐鑫信息代理商ESP-IDF开发环境搭建,本文首先介绍 ESP32-C3 的官方软件开发框架 ESP-IDF(包含开发环境),以及在不同计算机操作系统上搭建开发环境的方法:然后以一个典型工程为例,介绍 ESP-IDF 代码工程结构、编译系统,以及相关开发工具的使用方法;后演示示例代码的实际编译和运行过程,详细解读不同环节的输出信息。 ESP-IDF概述 ESP-IDF(EspressifIoT Development Framework) 是ESP32-C3无线路由芯片乐鑫信息代理商提供的一站式物联网开发框架它以C/C++为主要的开发语言,支持 Linux、Mac、Windows 等主流操作系统下的交叉编译提供的示例程序均是基于 ESP-IDF 搭建的,具有以下特性: (1)包含 ESP32、ESP32-S2、ESP32-C3 等系列的SoC 系统级驱动,主要包括外设底层 LL(LowLevel)库、HAL (Hardware Abstraction Layer)库、RTOS 支持和上层驱动软件等。(2)包含物联网开发必要的基础组件,主要包括 HTTP、MQTT 等多种网络协议栈,可支持动态调频的电源管理框架,以及 Flash 加密方案和 Secure Boot 方案等。(3)提供了开发和量产过程中常用的构建、烧录和调试工具 (见图4-1),例如基于 CMake 的构建系统、基于 GCC 的交叉编译工具链、基于 OpenOCD 的JTAG 调试工具等。值得注意的是,ESP32-C3无线路由芯片乐鑫信息代理商ESP-IDF 代码主要遵守 Apache 2.0开源协议,在遵守开源协议的前提下,用户可以不受限制地进行个人或商业软件开发,并且免费拥有永久的专利许可,无须开源修改后的源代码。 ESP-IDF 版本介绍 ESP-IDF代码在GitHub 上开源,目前有v3、v4和v5三个主要版本,每个主要版本通常包含多个不同的子版本,如v4.2、v4.3 等。ESP32-C3无线路由芯片乐鑫信息代理商还为每个已发布的子版本提供30个月的 bug修复、安全修复支持,因此一般还会发布子版本的修订版本,如v4.3.1、4.2.2等。不同版本的ESP-IDF对乐鑫芯片的支持状态如表4-1所示,其中 preview 表示提供预览版本的支持,预览版本可能缺少关键的功能或文档,supported 表示提供正式版本的支持。 主要版本的迭代往往伴随着框架结构的调整和编译系统的更新,如 v3.* 到 v4.* 的主要变化是构建系统从Make 逐渐迁移到 CMake; 子版本的选代一般意味着新增功能或新增芯片支持还需要注意稳定版本和 GitHub 分支的区别和联系,如上所述的带有 v** 或**.* 标签的版本均为稳定版本,稳定版本已通过乐鑫科技的完整内部测试,同一版本下的代码、工具链、发布文档在固定后不再变更。而 GitHub 分支(如 release/v4.3 分支)则几乎每天都会有新的代码提交,因此,同在该分支下的两份代码可能是不同的,需要开发者及时更新。 乐鑫科技 ESP-IDF Git 的工作流程如下 新的改动总是在 master 分支(主开发分支) 上进行的,master 分支上的 ESP-IDF 版本带有-dev标签,表示正在开发中,如v4.3-dev。master 分支上的改动将首先在乐鑫科装的内部仓库中进行代码审阅与测试,然后在自动化测试完成后推至 GitHub。新版本一且完成特性开发(在 master 分支上进行)并达到进入 Beta 测试的标准,则会将个新版本切换至一个新分支(如 release/v4.3)。此外,这个新分支还会加上预发布标签(如v4.3-beta1)。开发者可以在 GitHub 平台上查看ESP32-C3无线路由芯片乐鑫信息代理商ESP-IDF 的完整分支列表和标签列表Beta 版本(预发布版本)可能仍存在大量已知问题,随着对 Beta 版本的不断测试,bug 修复将同时增加至该版本分支和 master 分支,而 master 分支可能也已经开始为下个版本开发新特性了。当测试快结束时,该发布分支上将增加一个 rc 标签,表示候选发布 (ReleaseCandidate),如 v4.3-rc1,此时该分支仍属于预发布版本。 如果一直未发现或未报告重大 bug,则该预发布版本将终增加主要版本 (如 5.0)或次要版本标记(如v4.3),成为正式发布版本,并体现在发布说明页面中。后续,该版本中发现的bug 都将在该发布分支上进行修复。在人工测试完成后,该分支将增加一个 Bugfix 版本标签(如 v4.3.2),并体现在发布说明页面中。 选择一个合适的版本 由于ESP-IDF从v4.3版本正式开始对 ESP32-C3 提供支持,在撰写时还未正式发布 v4.4版本,因此使用的是 v4.3.2 修订版本。当阅读本文时,可能已经发布了 v4.4 版本或更新的版本,对于版本的选择,我们建议: (1)对于入门开发者,推荐选择稳定的 v4.3 版本及其修订版本,与示例版本保持一致。 (2)如果有量产需求,则推荐使用新的稳定版本,以便获得及时的技术支持。 (3)如果需要尝试ESP32-C3无线路由芯片乐鑫信息代理商新芯片或者预研产品新功能,请使用 master 分支,新版本包含所有的新特性,但存在已知或未知的 bug。 (4)如果使用的稳定版本没有新特性,又想降低使用 master 分支的风险,请使用对应的发布分支,如 release/v4.4 分支(ESP-IDF GitHub 会先创建 release/v4.4 分支,等完成全部功能的开发和测试后,再基于该分支的某一历史节点发布稳定的 v4.4 版本)。 ESP-IDF SDK目录总览 ESP32-C3无线路由芯片乐鑫信息代理商ESP-IDF SDK 包含esp-idf 和.espressif 两个主要目录,前者主要包含 ESP-IDF 仓库源代码文件和编译脚本,后者主要保存编译工具链等软件。熟悉这两个目录,有助于开发者更好地利用已有的资源,加快开发过程。 (1)ESP-IDF 仓库代码目录 (~/esp/esp-idf)  1)组件目录 components。该目录是 ESP-IDF 的核心目录,集成了大量的核心软件组件,任何一个工程代码都无法完全脱离该目录的组件进行编译。该目录包括对多款乐鑫芯片的驱动支持,从外设底层 LL 库、HAL 库接口,到上层 Driver、VFS 层支持,都能找到对应的组件,以供开发者进行不同层级的开发;ESP32-C3无线路由芯片乐鑫信息代理商ESP-IDF 还适配了多种标准网络协议栈,如 TCP/IP、HTTP、MQTT、WebSocket 等,开发者可以使用 Socket 等自己熟悉的接口完成网络应用的开发。组件作为一个功能完整的模块,可以方便地集成在应用程序中。
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