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兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F450VIT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F450VIT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F450xx ARM® Cortex®-M4 32-bit MCU Datasheet Device information Table 1. GD32F450xx devices features and peripheral list   Part Number GD32F450xx   VE VG VI VK ZE ZG ZI ZK IG II IK Flash Code Area (KB) 512 512 256 512 512 512 256 512 512 256 512   Data Area (KB) 0 512 1792 2560 0 512 1792 2560 512 1792 2560   Total (KB) 512 1024 2048 3072 512 1024 2048 3072 1024 2048 3072 SRAM (KB) 256 256 512 256 256 256 512 256 256 512 256 Timers 16-bit GPTM 8 8 8 8 8 8 8 8 8 8 8   32-bit GPTM 2 2 2 2 2 2 2 2 2 2 2   Adv. 16-bit TM 2 2 2 2 2 2 2 2 2 2 2   Basic TM 2 2 2 2 2 2 2 2 2 2 2   SysTick 1 1 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 1 1 1 Connectivity USART+UART 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4   I2C 3 3 3 3 3 3 3 3 3 3 3   SPI/I2S 5/2 5/2 5/2 5/2 6/2 6/2 6/2 6/2 6/2 6/2 6/2   SDIO 1 1 1 1 1 1 1 1 1 1 1   CAN 2.0B 2 2 2 2 2 2 2 2 2 2 2   USB OTG FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS   Ethernet MAC 1 1 1 1 1 1 1 1 1 1 1   TFT-LCD 1 1 1 1 1 1 1 1 1 1 1   Digital Camera 1 1 1 1 1 1 1 1 1 1 1 GPIO 82 82 82 82 114 114 114 114 140 140 140 EXMC/SDRAM 1/0 1/0 1/0 1/0 1/1 1/1 1/1 1/1 1/1 1/1 1/1 ADC Unit (CHs) 3(16) 3(16) 3(16) 3(16) 3(24) 3(24) 3(24) 3(24) 3(24) 3(24) 3(24) DAC 2 2 2 2 2 2 2
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F450VIT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F450xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

Device information

Table 1. GD32F450xx devices features and peripheral list

 

Part Number

GD32F450xx

 

VE

VG

VI

VK

ZE

ZG

ZI

ZK

IG

II

IK

Flash

Code Area (KB)

512

512

256

512

512

512

256

512

512

256

512

 

Data Area (KB)

0

512

1792

2560

0

512

1792

2560

512

1792

2560

 

Total (KB)

512

1024

2048

3072

512

1024

2048

3072

1024

2048

3072

SRAM (KB)

256

256

512

256

256

256

512

256

256

512

256

Timers

16-bit GPTM

8

8

8

8

8

8

8

8

8

8

8

 

32-bit GPTM

2

2

2

2

2

2

2

2

2

2

2

 

Adv. 16-bit TM

2

2

2

2

2

2

2

2

2

2

2

 

Basic TM

2

2

2

2

2

2

2

2

2

2

2

 

SysTick

1

1

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

1

1

Connectivity

USART+UART

4+4

4+4

4+4

4+4

4+4

4+4

4+4

4+4

4+4

4+4

4+4

 

I2C

3

3

3

3

3

3

3

3

3

3

3

 

SPI/I2S

5/2

5/2

5/2

5/2

6/2

6/2

6/2

6/2

6/2

6/2

6/2

 

SDIO

1

1

1

1

1

1

1

1

1

1

1

 

CAN 2.0B

2

2

2

2

2

2

2

2

2

2

2

 

USB OTG

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

 

Ethernet MAC

1

1

1

1

1

1

1

1

1

1

1

 

TFT-LCD

1

1

1

1

1

1

1

1

1

1

1

 

Digital Camera

1

1

1

1

1

1

1

1

1

1

1

GPIO

82

82

82

82

114

114

114

114

140

140

140

EXMC/SDRAM

1/0

1/0

1/0

1/0

1/1

1/1

1/1

1/1

1/1

1/1

1/1

ADC Unit (CHs)

3(16)

3(16)

3(16)

3(16)

3(24)

3(24)

3(24)

3(24)

3(24)

3(24)

3(24)

DAC

2

2

2

2

2

2

2

2

2

2

2

Package

LQFP100

LQFP144

BGA176

 

Memory map

Figure 5. GD32F450xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

External Device

 

 

 

AHB

matrix

0xC000 0000 - 0xDFFF FFFF

EXMC - SDRAM

 

 

0xA000 1000 - 0xBFFF FFFF

Reserved

 

 

0xA000 0000 - 0xA000 0FFF

EXMC - SWREG

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC - NOR/PSRAM/SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

AHB2

0x5006 0C00 - 0x5FFF FFFF

Reserved

 

 

0x5006 0800 - 0x5006 0BFF

TRNG

 

 

0x5005 0400 - 0x5006 07FF

Reserved

 

 

0x5005 0000 - 0x5005 03FF

DCI

 

 

0x5004 0000 - 0x5004 FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB1

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

USBHS

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

IPA

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

DMA1

 

 

0x4002 6000 - 0x4002 63FF

DMA0

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

BKPSRAM

 

 

0x4002 3C00 - 0x4002 3FFF

FMC

 

 

0x4002 3800 - 0x4002 3BFF

RCU

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

GPIOI

 

 

0x4002 1C00 - 0x4002 1FFF

GPIOH

 

 

0x4002 1800 - 0x4002 1BFF

GPIOG

 

 

0x4002 1400 - 0x4002 17FF

GPIOF

 

 

0x4002 1000 - 0x4002 13FF

GPIOE

 

 

0x4002 0C00 - 0x4002 0FFF

GPIOD

 

 

0x4002 0800 - 0x4002 0BFF

GPIOC

 

 

0x4002 0400 - 0x4002 07FF

GPIOB

 

 

0x4002 0000 - 0x4002 03FF

GPIOA

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 6C00 - 0x4001 FFFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

TLI

 

 

0x4001 5800 - 0x4001 67FF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

SPI5

 

 

0x4001 5000 - 0x4001 53FF

SPI4

 

 

0x4001 4C00 - 0x4001 4FFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER10

 

 

0x4001 4400 - 0x4001 47FF

TIMER9

 

 

0x4001 4000 - 0x4001 43FF

TIMER8

 

 

0x4001 3C00 - 0x4001 3FFF

EXTI

 

 

0x4001 3800 - 0x4001 3BFF

SYSCFG

 

 

0x4001 3400 - 0x4001 37FF

SPI3

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

SDIO

 

 

0x4001 2400 - 0x4001 2BFF

Reserved

 

 

0x4001 2000 - 0x4001 23FF

ADC

 

 

0x4001 1800 - 0x4001 1FFF

Reserved

 

 

0x4001 1400 - 0x4001 17FF

USART5

 

 

0x4001 1000 - 0x4001 13FF

USART0

 

 

0x4001 0800 - 0x4001 0FFF

Reserved

 

 

0x4001 0400 - 0x4001 07FF

TIMER7

 

 

0x4001 0000 - 0x4001 03FF

TIMER0

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 C800 - 0x4000 FFFF

Reserved

 

 

0x4000 C400 - 0x4000 C7FF

IVREF

 

 

0x4000 8000 - 0x4000 C3FF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

UART7

 

 

0x4000 7800 - 0x4000 7BFF

UART6

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

CTC

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

I2C2

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 4000 - 0x4000 43FF

I2S2_add

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

I2S1_add

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

SRAM

 

 

AHB

matrix

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2003 0000 - 0x2006 FFFF

SRAM3(256KB)

 

 

0x2002 0000 - 0x2002 FFFF

SRAM2(64KB)

 

 

0x2001 C000 - 0x2001 FFFF

SRAM1(16KB)

 

 

0x2000 0000 - 0x2001 BFFF

SRAM0(112KB)

 

 

 

 

 

 

 

 

Code

 

 

 

 

 

 

 

 

AHB

matrix

0x1FFF C010 - 0x1FFF FFFF

Reserved

 

 

0x1FFF C000 - 0x1FFF C00F

Option bytes(Bank 0)

 

 

0x1FFF 7A10 - 0x1FFF BFFF

Reserved

 

 

0x1FFF 7800 - 0x1FFF 7A0F

OTP(528B)

 

 

0x1FFF 0000 - 0x1FFF 77FF

Boot loader(30KB)

 

 

0x1FFE C010 - 0x1FFE FFFF

Reserved

 

 

0x1FFE C000 - 0x1FFE C00F

Option bytes(Bank 1)

 

 

0x1001 0000 - 0x1FFE BFFF

Reserved

 

 

0x1000 0000 - 0x1000 FFFF

TCMSRAM(64KB)

 

 

0x0830 0000 - 0x0FFF FFFF

Reserved

 

 

0x0800 0000 - 0x082F FFFF

Main Flash(3072KB)

 

 

 

0x0000 0000 - 0x07FF FFFF

Aliased to

the boot device

Pin definitions

Table 2. GD32F450xx pin definitions

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

PE2

 

A2

 

1

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECLK, SPI3_SCK, ETH_MII_TXD3, EXMC_A23, EVENTOUT

 

PE3

 

A1

 

2

 

2

 

I/O

 

5VT

Default: PE3

Alternate:TRACED0, EXMC_A19, EVENTOUT

 

PE4

 

B1

 

3

 

3

 

I/O

 

5VT

Default: PE4

Alternate:TRACED1, SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT

 

PE5

 

B2

 

4

 

4

 

I/O

 

5VT

Default: PE5

Alternate:TRACED2, TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT

 

PE6

 

B3

 

5

 

5

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3, TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT

VBAT

C1

6

6

P

-

Default: VBAT

 

PI8

 

D2

 

-

 

-

 

I/O

 

5VT

Default: PI8

Alternate: EVENTOUT

Additional:RTC_TAMP1, RTC_TAMP0, RTC_TS

PC13-

TAMPER- RTC

 

D1

 

7

 

7

 

I/O

 

5VT

Default: PC13 Alternate: EVENTOUT

Additional: RTC_TAMP0, RTC_OUT, RTC_TS

 

PC14- OSC32IN

 

E1

 

8

 

8

 

I/O

 

5VT

Default: PC14

Alternate: EVENTOUT Additional: OSC32IN

 

PC15- OSC32OUT

 

F1

 

9

 

9

 

I/O

 

5VT

Default: PC15 Alternate: EVENTOUT

Additional: OSC32OUT

 

PI9

 

D3

 

-

 

-

 

I/O

 

5VT

Default: PI9

Alternate: CAN0_RX, EXMC_D30, TLI_VSYNC, EVENTOUT

 

PI10

 

E3

 

-

 

-

 

I/O

 

5VT

Default: PI10

Alternate: ETH_MII_RX_ER, EXMC_D31, TLI_HSYNC, EVENTOUT

 

PI11

 

E4

 

-

 

-

 

I/O

 

5VT

Default: PI11

Alternate: USBHS_ULPI_DIR, EVENTOUT

VSS

F2

-

-

P

-

Default: VSS

VDD

F3

-

-

P

-

Default: VDD

 

PF0

 

E2

 

10

 

-

 

I/O

 

5VT

Default: PF0

Alternate: I2C1_SDA, EXMC_A0, EVENTOUT, CTC_SYNC

PF1

H3

11

-

I/O

5VT

Default: PF1

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

 

 

 

 

 

Alternate: I2C1_SCL, EXMC_A1, EVENTOUT

 

PF2

 

H2

 

12

 

-

 

I/O

 

5VT

Default: PF2

Alternate: I2C1_SMBA, EXMC_A2, EVENTOUT

 

PF3

 

J2

 

13

 

-

 

I/O

 

5VT

Default: PF3

Alternate: EXMC_A3, EVENTOUT, I2C1_TXFRAME

Additional: ADC2_IN9

 

PF4

 

J3

 

14

 

-

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4, EVENTOUT Additional: ADC2_IN14

 

PF5

 

K3

 

15

 

-

 

I/O

 

5VT

Default: PF5

Alternate: EXMC_A5, EVENTOUT Additional: ADC2_IN15

VSS

G2

16

10

P

-

Default: VSS

VDD

G3

17

11

P

-

Default: VDD

 

 

PF6

 

 

K2

 

 

18

 

 

-

 

 

I/O

 

 

5VT

Default: PF6

Alternate:TIMER9_CH0, SPI4_NSS, UART6_RX, EXMC_NIORD, EVENTOUT

Additional: ADC2_IN4

 

 

PF7

 

 

K1

 

 

19

 

 

-

 

 

I/O

 

 

5VT

Default: PF7

Alternate:TIMER10_CH0, SPI4_SCK, UART6_TX, EXMC_NREG, EVENTOUT

Additional: ADC2_IN5

 

PF8

 

L3

 

20

 

-

 

I/O

 

5VT

Default: PF8

Alternate:SPI4_MISO, TIMER12_CH0, EXMC_NIOWR, EVENTOUT

Additional: ADC2_IN6

 

PF9

 

L2

 

21

 

-

 

I/O

 

5VT

Default: PF9

Alternate: SPI4_MOSI, TIMER13_CH0, EXMC_CD, EVENTOUT

Additional: ADC2_IN7

 

PF10

 

L1

 

22

 

-

 

I/O

 

5VT

Default: PF10

Alternate: EXMC_INTR, DCI_D11, TLI_DE, EVENTOUT

Additional: ADC2_IN8

 

PH0

 

G1

 

23

 

12

 

I/O

 

5VT

Default: PH0, OSCIN Alternate: EVENTOUT

Additional: OSCIN

 

PH1

 

H1

 

24

 

13

 

I/O

 

5VT

Default: PH1, OSCOUT Alternate: EVENTOUT

Additional: OSCOUT

NRST

J1

25

14

-

-

Default: NRST

 

PC0

 

M2

 

26

 

15

 

I/O

 

5VT

Default: PC0

Alternate: USBHS_ULPI_STP, EXMC_SDNWE, EVENTOUT

Additional: ADC012_IN10

 

PC1

 

M3

 

27

 

16

 

I/O

 

5VT

Default: PC1

Alternate:SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ETH_MDC,

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

 

 

 

 

 

EVENTOUT

Additional: ADC012_IN11

 

 

PC2

 

 

M4

 

 

28

 

 

17

 

 

I/O

 

 

5VT

Default: PC2

Alternate:SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ETH_MII_TXD2, EXMC_SDNE0, EVENTOUT

Additional: ADC012_IN12

 

 

PC3

 

 

M5

 

 

29

 

 

18

 

 

I/O

 

 

5VT

Default: PC3

Alternate:SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ETH_MII_TX_CLK, EXMC_SDCKE0, EVENTOUT

Additional: ADC012_IN13

VDD

G3

30

19

P

-

Default: VDD

VSSA

M1

31

20

P

-

Default: VSSA

VREFN

N1

-

-

P

-

Default: VREF-

VREFP

P1

32

21

P

-

Default: VREF+

VDDA

R1

33

22

P

-

Default: VDDA

 

 

PA0-WKUP

 

 

N3

 

 

34

 

 

23

 

 

I/O

 

 

5VT

Default: PA0

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, ETH_MII_CRS, EVENTOUT

Additional: ADC012_IN0, WKUP

 

 

PA1

 

 

N2

 

 

35

 

 

24

 

 

I/O

 

 

5VT

Default: PA1

Alternate:TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS, UART3_RX, ETH_MII_RX_CLK, ETH_RMII_REF_CLK, EVENTOUT

Additional: ADC012_IN1

 

 

PA2

 

 

P2

 

 

36

 

 

25

 

 

I/O

 

 

5VT

Default: PA2

Alternate:TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, ETH_MDIO, EVENTOUT

Additional: ADC012_IN2

 

PH2

 

F4

 

-

 

-

 

I/O

 

5VT

Default: PH2

Alternate: ETH_MII_CRS, EXMC_SDCKE0, TLI_R0, EVENTOUT

 

PH3

 

G4

 

-

 

-

 

I/O

 

5VT

Default: PH3

Alternate: ETH_MII_COL, EXMC_SDNE0, TLI_R1, EVENTOUT, I2C1_TXFRAME

 

PH4

 

H4

 

-

 

-

 

I/O

 

5VT

Default: PH4

Alternate: I2C1_SCL, USBHS_ULPI_NXT, EVENTOUT

 

PH5

 

J4

 

-

 

-

 

I/O

 

5VT

Default: PH5

Alternate: I2C1_SDA, SPI4_NSS, EXMC_SDNWE, EVENTOUT

 

 

PA3

 

 

R2

 

 

37

 

 

26

 

 

I/O

 

 

5VT

Default: PA3

Alternate:TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, ETH_MII_COL, TLI_B5, EVENTOUT

Additional: ADC012_IN3

VSS

-

38

27

P

-

Default: VSS

NC

L4

-

-

-

-

-

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

VDD

K4

39

28

P

-

Default: VDD

 

 

PA4

 

 

N4

 

 

40

 

 

29

 

 

I/O

 

 

TTa

Default: PA4

Alternate:SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, TLI_VSYNC, EVENTOUT

Additional: ADC01_IN4, DAC_OUT0

 

 

PA5

 

 

P4

 

 

41

 

 

30

 

 

I/O

 

 

TTa

Default: PA5

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT

Additional: ADC01_IN5, DAC_OUT1

 

 

PA6

 

 

P3

 

 

42

 

 

31

 

 

I/O

 

 

5VT

Default: PA6

Alternate:TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, TLI_G2, EVENTOUT

Additional: ADC01_IN6

 

 

PA7

 

 

R3

 

 

43

 

 

32

 

 

I/O

 

 

5VT

Default: PA7

Alternate:TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, ETH_MII_RX_DV, ETH_RMII_CRS_DV, EXMC_SDNWE, EVENTOUT

Additional: ADC01_IN7

 

 

PC4

 

 

N5

 

 

44

 

 

33

 

 

I/O

 

 

5VT

Default: PC4

Alternate: ETH_MII_RXD0, ETH_RMII_RXD0, EXMC_SDNE0, EVENTOUT

Additional: ADC01_IN14

 

 

PC5

 

 

P5

 

 

45

 

 

34

 

 

I/O

 

 

5VT

Default: PC5

Alternate:USART2_RX, ETH_MII_RXD1, ETH_RMII_RXD1, EXMC_SDCKE0, EVENTOUT

Additional: ADC01_IN15

 

 

PB0

 

 

R5

 

 

46

 

 

35

 

 

I/O

 

 

5VT

Default: PB0

Alternate:TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI4_SCK, SPI2_MOSI, I2S2_SD, TLI_R3, USBHS_ULPI_D1, ETH_MII_RXD2, SDIO_D1, EVENTOUT

Additional: ADC01_IN8, IREF

 

 

PB1

 

 

R4

 

 

47

 

 

36

 

 

I/O

 

 

5VT

Default: PB1

Alternate:TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, SPI4_NSS, TLI_R6, USBHS_ULPI_D2, ETH_MII_RXD3, SDIO_D2, EVENTOUT

Additional: ADC01_IN9

 

PB2

 

M6

 

48

 

37

 

I/O

 

5VT

Default: PB2, BOOT1

Alternate:TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT

 

PF11

 

R6

 

49

 

-

 

I/O

 

5VT

Default: PF11

Alternate: SPI4_MOSI, EXMC_SDNRAS, DCI_D12, EVENTOUT

PF12

P6

50

-

I/O

5VT

Default: PF12

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

 

 

 

 

 

Alternate: EXMC_A6, EVENTOUT

VSS

M8

51

-

P

-

Default: VSS

VDD

N8

52

-

P

-

Default: VDD

 

PF13

 

N6

 

53

 

-

 

I/O

 

5VT

Default: PF13

Alternate: EXMC_A7, EVENTOUT

 

PF14

 

R7

 

54

 

-

 

I/O

 

5VT

Default: PF14

Alternate: EXMC_A8, EVENTOUT

 

PF15

 

P7

 

55

 

-

 

I/O

 

5VT

Default: PF15

Alternate: EXMC_A9, EVENTOUT

 

PG0

 

N7

 

56

 

-

 

I/O

 

5VT

Default: PG0

Alternate: EXMC_A10, EVENTOUT

 

PG1

 

M7

 

57

 

-

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11, EVENTOUT

 

PE7

 

R8

 

58

 

38

 

I/O

 

5VT

Default: PE7

Alternate: TIMER0_ETI, UART6_RX, EXMC_D4, EVENTOUT

 

PE8

 

P8

 

59

 

39

 

I/O

 

5VT

Default: PE8

Alternate: TIMER0_CH0_ON, UART6_TX, EXMC_D5, EVENTOUT

 

PE9

 

P9

 

60

 

40

 

I/O

 

5VT

Default: PE9

Alternate: TIMER0_CH0, EXMC_D6, EVENTOUT

VSS

M9

61

-

P

-

Default: VSS

VDD

N9

62

-

P

-

Default: VDD

 

PE10

 

R9

 

63

 

41

 

I/O

 

5VT

Default: PE10

Alternate: TIMER0_CH1_ON, EXMC_D7, EVENTOUT

 

PE11

 

P10

 

64

 

42

 

I/O

 

5VT

Default: PE11

Alternate:TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8, TLI_G3, EVENTOUT

 

PE12

 

R10

 

65

 

43

 

I/O

 

5VT

Default: PE12

Alternate:TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9, TLI_B4, EVENTOUT

 

PE13

 

N11

 

66

 

44

 

I/O

 

5VT

Default: PE13

Alternate:TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10, TLI_DE, EVENTOUT

 

PE14

 

P11

 

67

 

45

 

I/O

 

5VT

Default: PE14

Alternate:TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11, TLI_PIXCLK, EVENTOUT

 

PE15

 

R11

 

68

 

46

 

I/O

 

5VT

Default: PE15

Alternate: TIMER0_BRKIN, EXMC_D12, TLI_R7, EVENTOUT

 

 

PB10

 

 

R12

 

 

69

 

 

47

 

 

I/O

 

 

5VT

Default: PB10

Alternate:TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK,

USART2_TX, USBHS_ULPI_D3, ETH_MII_RX_ER, SDIO_D7, TLI_G4, EVENTOUT

 

PB11

 

R13

 

70

 

48

 

I/O

 

5VT

Default: PB11

Alternate:TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX,

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

 

 

 

 

 

USBHS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TLI_G5,

EVENTOUT

NC

M10

71

49

P

-

Default: VCORE

VDD

N10

72

50

P

-

Default: VDD

 

PH6

 

M11

 

-

 

-

 

I/O

 

5VT

Default: PH6

Alternate:I2C1_SMBA, SPI4_SCK, TIMER11_CH0, ETH_MII_RXD2, EXMC_SDNE1, DCI_D8, EVENTOUT

 

PH7

 

N12

 

-

 

-

 

I/O

 

5VT

Default: PH7

Alternate:I2C2_SCL, SPI4_MISO, ETH_MII_RXD3, EXMC_SDCKE1, DCI_D9, EVENTOUT

 

PH8

 

M12

 

-

 

-

 

I/O

 

5VT

Default: PH8

Alternate: I2C2_SDA, EXMC_D16, DCI_HSYNC, TLI_R2, EVENTOUT

 

PH9

 

M13

 

-

 

-

 

I/O

 

5VT

Default: PH9

Alternate:I2C2_SMBA, TIMER11_CH1, EXMC_D17, DCI_D0, TLI_R3, EVENTOUT

 

PH10

 

L13

 

-

 

-

 

I/O

 

5VT

Default: PH10

Alternate:TIMER4_CH0, EXMC_D18, DCI_D1, TLI_R4, EVENTOUT, I2C2_TXFRAME

 

PH11

 

L12

 

-

 

-

 

I/O

 

5VT

Default: PH11

Alternate: TIMER4_CH1, EXMC_D19, DCI_D2, TLI_R5, EVENTOUT

 

PH12

 

K12

 

-

 

-

 

I/O

 

5VT

Default: PH12

Alternate: TIMER4_CH2, EXMC_D20, DCI_D3, TLI_R6, EVENTOUT

VSS

H12

-

-

P

-

Default: VSS

VDD

J12

-

-

P

-

Default: VDD

 

 

PB12

 

 

P12

 

 

73

 

 

51

 

 

I/O

 

 

5VT

Default: PB12

Alternate:TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, ETH_MII_TXD0, ETH_RMII_TXD0, USBHS_ID, EVENTOUT

 

 

PB13

 

 

P13

 

 

74

 

 

52

 

 

I/O

 

 

5VT

Default: PB13

Alternate:TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, SPI3_SCK, USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT, I2C1_TXFRAME

Additional: USBHS_VBUS

 

 

PB14

 

 

R14

 

 

75

 

 

53

 

 

I/O

 

 

5VT

Default: PB14

Alternate:TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM,

EVENTOUT

 

PB15

 

R15

 

76

 

54

 

I/O

 

5VT

Default: PB15

Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT

 

PD8

 

P15

 

77

 

55

 

I/O

 

5VT

Default: PD8

Alternate: USART2_TX, EXMC_D13, EVENTOUT

PD9

P14

78

56

I/O

5VT

Default: PD9

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

 

 

 

 

 

Alternate: USART2_RX, EXMC_D14, EVENTOUT

 

PD10

 

N15

 

79

 

57

 

I/O

 

5VT

Default: PD10

Alternate: USART2_CK, EXMC_D15, TLI_B3, EVENTOUT

 

PD11

 

N14

 

80

 

58

 

I/O

 

5VT

Default: PD11

Alternate: USART2_CTS, EXMC_A16, EVENTOUT

 

PD12

 

N13

 

81

 

59

 

I/O

 

5VT

Default: PD12

Alternate: TIMER3_CH0, USART2_RTS, EXMC_A17, EVENTOUT

 

PD13

 

M15

 

82

 

60

 

I/O

 

5VT

Default: PD13

Alternate: TIMER3_CH1, EXMC_A18, EVENTOUT

VSS

-

83

-

P

-

Default: VSS

VDD

J13

84

-

P

-

Default: VDD

 

PD14

 

M14

 

85

 

61

 

I/O

 

5VT

Default: PD14

Alternate: TIMER3_CH2, EXMC_D0, EVENTOUT

 

PD15

 

L14

 

86

 

62

 

I/O

 

5VT

Default: PD15

Alternate: TIMER3_CH3, EXMC_D1, EVENTOUT, CTC_SYNC

 

PG2

 

L15

 

87

 

-

 

I/O

 

5VT

Default: PG2

Alternate:EXMC_A12, EVENTOUT

 

PG3

 

K15

 

88

 

-

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13, EVENTOUT

 

PG4

 

K14

 

89

 

-

 

I/O

 

5VT

Default: PG4

Alternate: EXMC_A14, EVENTOUT

 

PG5

 

K13

 

90

 

-

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15, EVENTOUT

 

PG6

 

J15

 

91

 

-

 

I/O

 

5VT

Default: PG6

Alternate: EXMC_INT1, DCI_D12, TLI_R7, EVENTOUT

 

PG7

 

J14

 

92

 

-

 

I/O

 

5VT

Default: PG7

Alternate: USART5_CK, EXMC_INT2, DCI_D13, TLI_PIXCLK, EVENTOUT

 

PG8

 

H14

 

93

 

-

 

I/O

 

5VT

Default: PG8

Alternate:SPI5_NSS, USART5_RTS, ETH_PPS_OUT, EXMC_SDCLK, EVENTOUT

VSS

G12

94

-

P

-

Default: VSS

VDD

H13

95

-

P

-

Default: VDD

 

PC6

 

H15

 

96

 

63

 

I/O

 

5VT

Default: PC6

Alternate:TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, TLI_HSYNC, EVENTOUT

 

PC7

 

G15

 

97

 

64

 

I/O

 

5VT

Default: PC7

Alternate:TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, TLI_G6, EVENTOUT

 

PC8

 

G14

 

98

 

65

 

I/O

 

5VT

Default: PC8

Alternate:TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT

PC9

F14

99

66

I/O

5VT

Default: PC9

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

 

 

 

 

 

Alternate:CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA,

I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT

 

PA8

 

F15

 

100

 

67

 

I/O

 

5VT

Default: PA8

Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, TLI_R6, EVENTOUT, CTC_SYNC

 

 

PA9

 

 

E15

 

 

101

 

 

68

 

 

I/O

 

 

5VT

Default: PA9

Alternate:TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT

Additional: USBFS_VBUS

 

PA10

 

D15

 

102

 

69

 

I/O

 

5VT

Default: PA10

Alternate:TIMER0_CH2, SPI4_MOSI, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME

 

PA11

 

C15

 

103

 

70

 

I/O

 

5VT

Default: PA11

Alternate:TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, TLI_R4, EVENTOUT

 

PA12

 

B15

 

104

 

71

 

I/O

 

5VT

Default: PA12

Alternate:TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, TLI_R5, EVENTOUT

 

PA13

 

A15

 

105

 

72

 

I/O

 

5VT

Default: JTMS, SWDIO, PA13

Alternate: EVENTOUT

NC

F13

106

73

-

-

-

VSS

F12

107

74

P

-

Default: VSS

VDD

G13

108

75

P

-

Default: VDD

 

PH13

 

E12

 

-

 

-

 

I/O

 

5VT

Default: PH13

Alternate: TIMER7_CH0_ON, CAN0_TX, EXMC_D21, TLI_G2, EVENTOUT

 

PH14

 

E13

 

-

 

-

 

I/O

 

5VT

Default: PH14

Alternate: TIMER7_CH1_ON, EXMC_D22, DCI_D4, TLI_G3, EVENTOUT

 

PH15

 

D13

 

-

 

-

 

I/O

 

5VT

Default: PH15

Alternate: TIMER7_CH2_ON, EXMC_D23, DCI_D11,TLI_G4, EVENTOUT

 

PI0

 

E14

 

 

-

 

I/O

 

5VT

Default: PI0

Alternate:TIMER4_CH3, SPI1_NSS, I2S1_WS, EXMC_D24, DCI_D13, TLI_G5, EVENTOUT

 

PI1

 

D14

 

-

 

-

 

I/O

 

5VT

Default: PI1

Alternate:SPI1_SCK, I2S1_CK, EXMC_D25, DCI_D8, TLI_G6, EVENTOUT

 

PI2

 

C14

 

-

 

-

 

I/O

 

5VT

Default: PI2

Alternate:TIMER7_CH3, SPI1_MISO, I2S1_ADD_SD, EXMC_D26, DCI_D9, TLI_G7, EVENTOUT

 

PI3

 

C13

 

-

 

-

 

I/O

 

5VT

Default: PI3

Alternate:TIMER7_ETI, SPI1_MOSI, I2S1_SD, EXMC_D27, DCI_D10, EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

VSS

D9

-

-

P

-

Default: VSS

VDD

C9

-

-

P

-

Default: VDD

 

PA14

 

A14

 

109

 

76

 

I/O

 

5VT

Default: JTCK, SWCLK, PA14

Alternate: EVENTOUT

 

PA15

 

A13

 

110

 

77

 

I/O

 

5VT

Default: JTDI, PA15

Alternate:TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT

 

PC10

 

B14

 

111

 

78

 

I/O

 

5VT

Default: PC10

Alternate:SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, TLI_R2, EVENTOUT

 

PC11

 

B13

 

112

 

79

 

I/O

 

5VT

Default: PC11

Alternate:I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT

 

PC12

 

A12

 

113

 

80

 

I/O

 

5VT

Default: PC12

Alternate:I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT

 

PD0

 

B12

 

114

 

81

 

I/O

 

5VT

Default: PD0

Alternate:SPI3_MISO, SPI2_MOSI, I2S2_SD, CAN0_RX, EXMC_D2, EVENTOUT

 

PD1

 

C12

 

115

 

82

 

I/O

 

5VT

Default: PD1

Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT

 

PD2

 

D12

 

116

 

83

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT

 

PD3

 

D11

 

117

 

84

 

I/O

 

5VT

Default: PD3

Alternate:TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT

 

PD4

 

D10

 

118

 

85

 

I/O

 

5VT

Default: PD4

Alternate: USART1_RTS, EXMC_NOE, EVENTOUT

 

PD5

 

C11

 

119

 

86

 

I/O

 

5VT

Default: PD5

Alternate: USART1_TX, EXMC_NWE, EVENTOUT

VSS

D8

120

-

P

-

Default: VSS

VDD

C8

121

-

P

-

Default: VDD

 

PD6

 

B11

 

122

 

87

 

I/O

 

5VT

Default: PD6

Alternate:SPI2_MOSI, I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT

 

PD7

 

A11

 

123

 

88

 

I/O

 

5VT

Default: PD7

Alternate: USART1_CK, EXMC_NE0, EXMC_NCE1, EVENTOUT

 

PG9

 

C10

 

124

 

-

 

I/O

 

5VT

Default: PG9

Alternate:USART5_RX, EXMC_NE1, EXMC_NCE2, DCI_VSYNC, EVENTOUT

 

PG10

 

B10

 

125

 

-

 

I/O

 

5VT

Default: PG10

Alternate:SPI5_IO2, TLI_G3, EXMC_NCE3_0, EXMC_NE2, DCI_D2, TLI_B2, EVENTOUT

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

PG11

 

B9

 

126

 

-

 

I/O

 

5VT

Default: PG11

Alternate:SPI5_IO3, SPI3_SCK, ETH_MII_TX_EN, ETH_RMII_TX_EN, EXMC_NCE3_1, DCI_D3, TLI_B3, EVENTOUT

 

PG12

 

B8

 

127

 

-

 

I/O

 

5VT

Default: PG12

Alternate:SPI5_MISO, SPI3_MISO, USART5_RTS, TLI_B4, EXMC_NE3, TLI_B1, EVENTOUT

 

PG13

 

A8

 

128

 

-

 

I/O

 

5VT

Default: PG13

Alternate:TRACED2, SPI5_SCK, SPI3_MOSI, USART5_CTS, ETH_MII_TXD0, ETH_RMII_TXD0, EXMC_A24, EVENTOUT

 

PG14

 

A7

 

129

 

-

 

I/O

 

5VT

Default: PG14

Alternate:TRACED3, SPI5_MOSI, SPI3_NSS, USART5_TX, ETH_MII_TXD1, ETH_RMII_TXD1, EXMC_A25, EVENTOUT

VSS

D7

130

-

P

-

Default: VSS

VDD

C7

131

-

P

-

Default: VDD

 

PG15

 

B7

 

132

 

-

 

I/O

 

5VT

Default: PG15

Alternate: USART5_CTS, EXMC_SDNCAS, DCI_D13, EVENTOUT

 

PB3

 

A10

 

133

 

89

 

I/O

 

5VT

Default: JTDO, PB3

Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT

 

PB4

 

A9

 

134

 

90

 

I/O

 

5VT

Default: JNTRST, PB4

Alternate:TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME

 

 

PB5

 

 

A6

 

 

135

 

 

91

 

 

I/O

 

 

5VT

Default: PB5

Alternate:TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ETH_PPS_OUT,

EXMC_SDCKE1, DCI_D10, EVENTOUT

 

PB6

 

B6

 

136

 

92

 

I/O

 

5VT

Default: PB6

Alternate:TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, EXMC_SDNE1, DCI_D5, EVENTOUT

 

PB7

 

B5

 

137

 

93

 

I/O

 

5VT

Default: PB7

Alternate:TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL, DCI_VSYNC, EVENTOUT

BOOT0

D6

138

94

I/O

5VT

Default: BOOT0

 

 

PB8

 

 

A5

 

 

139

 

 

95

 

 

I/O

 

 

5VT

Default: PB8

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0,

I2C0_SCL, SPI4_MOSI, CAN0_RX, ETH_MII_TXD3, SDIO_D4, DCI_D6, TLI_B6, EVENTOUT

 

 

PB9

 

 

B4

 

 

140

 

 

96

 

 

I/O

 

 

5VT

Default: PB9

Alternate:TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA,

SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, TLI_B7, EVENTOUT

 

PE0

 

A4

 

141

 

97

 

I/O

 

5VT

Default: PE0

Alternate: TIMER3_ETI, UART7_RX, EXMC_NBL0, DCI_D2, EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA176

LQFP144

LQFP100

 

 

 

 

PE1

 

A3

 

142

 

98

 

I/O

 

5VT

Default: PE1

Alternate: TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT

VSS

D5

-

99

P

-

Default: VSS

PDR_ON

C6

143

-

P

-

Default: PDR_ON

VDD

C5

144

100

P

-

Default: VDD

 

PI4

 

D4

 

-

 

-

 

I/O

 

5VT

Default: PI4

Alternate: TIMER7_BRKIN, EXMC_NBL2, DCI_D5, TLI_B4, EVENTOUT

 

PI5

 

C4

 

-

 

-

 

I/O

 

5VT

Default: PI5

Alternate: TIMER7_CH0, EXMC_NBL3, DCI_VSYNC, TLI_B5, EVENTOUT

 

PI6

 

C3

 

-

 

-

 

I/O

 

5VT

Default: PI6

Alternate: TIMER7_CH1, EXMC_D28, DCI_D6, TLI_B6, EVENTOUT

 

PI7

 

C2

 

-

 

-

 

I/O

 

5VT

Default: PI7

Alternate: TIMER7_CH2, EXMC_D29, DCI_D7, TLI_B7, EVENTOUT

Notes:
1.Type: I = input, O = output, P = power.
2.I/O Level: 5VT = 5 V tolerant.

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 200 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 3072 Kbytes of Flash memory, including code Flash and data Flash
512B of OTP (one-time programmable) memory
256 KB to 512 KB of SRAM

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and

accessed (R/W) at CPU clock speed with zero wait states. Up to 512 Kbytes of inner SRAM is composed of SRAM0 (112KB), SRAM1 (16KB), and SRAM2 (64KB) and SRAM3 (256KB)
that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex®-M4 core. The additional 4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the VDD power supply is down. The Figure of GD32F450xx memory map shows the memory map of the GD32F450xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 6 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal 30KB of information blocks for the boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART2, and USB Device FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option bytes.

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.6MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for external battery power supply (VBAT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

Two 12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for DMA1)
Support independent 8, 16, 32-bit memory and peripheral transfer
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO and DCI

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 140 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable

There are up to 140 general purpose I/O pins (GPIO) in GD32F450xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH15 and PI0 ~ PI11 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced-control timer (TM0 & TM7), eight 16-bit general-purpose timers (TM2, TM3, TM8 ~ TM13), two 32-bit general-purpose timers (TM1 & TM4) and two 16- bit basic timer (TM5 & TM6)
Up to 4 independent channels of PWM, output compare or input capture for each general- purpose timer (GPTM) and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog and window watchdog)

The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a