这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F307VGT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F307VGT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F307xx ARM® Cortex®-M4 32-bit MCU Datasheet General description The GD32F307xx device belongs to the mainstream line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F307xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1024 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 2.6 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss, two CANs, a USBFS and an ENET. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make GD32F307xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, communication networks, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, IoT and so on. Device information Table 2-1. GD32F307xx devices features and peripheral list   Part Number GD32F307xx   RC RE RG VC VE VG ZC ZE ZG Flash Code area (KB)   256   256   256   256   256   256   256   256   256   Data area (KB)   0   256   768   0   256   768   0   256   768   Total (KB) 256 512 1024 256 512 1024 256 512 1024 SRAM (KB) 96 96 96 96 96 96 96 96 96 Timers General timer(16-bit) 4 (1-4) 4 (1-4) 10 (1-4,8-13) 4 (1-4) 4 (1-4) 10 (1-4,8-13) 4 (1-4) 4 (1-4) 10 (1-4,8-13)   Advanced timer(16-bit) 1 (0) 2 (0,7) 2 (0,7) 1 (0) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7)   Basic timer(16-bit) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6)   SysTick 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 1 Connectivity   USART 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2)     UART 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4)   I2C 2 2 2
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F307VGT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F307xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

General description

The GD32F307xx device belongs to the mainstream line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support.
The GD32F307xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1024 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 2.6 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss, two CANs, a USBFS and an ENET.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make GD32F307xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, communication networks, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, IoT and so on.

Device information

Table 2-1. GD32F307xx devices features and peripheral list

 

Part Number

GD32F307xx

 

RC

RE

RG

VC

VE

VG

ZC

ZE

ZG

Flash

Code area

(KB)

 

256

 

256

 

256

 

256

 

256

 

256

 

256

 

256

 

256

 

Data area

(KB)

 

0

 

256

 

768

 

0

 

256

 

768

 

0

 

256

 

768

 

Total (KB)

256

512

1024

256

512

1024

256

512

1024

SRAM (KB)

96

96

96

96

96

96

96

96

96

Timers

General

timer(16-bit)

4

(1-4)

4

(1-4)

10

(1-4,8-13)

4

(1-4)

4

(1-4)

10

(1-4,8-13)

4

(1-4)

4

(1-4)

10

(1-4,8-13)

 

Advanced

timer(16-bit)

1

(0)

2

(0,7)

2

(0,7)

1

(0)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

Basic

timer(16-bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

SysTick

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

 

USART

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

 

UART

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

 

I2C

2

2

2

2

2

2

2

2

2

 

 

SPI/I2S

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

 

ENET

1

1

1

1

1

1

1

1

1

 

CAN

2

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

1

GPIO

51

51

51

80

80

80

112

112

112

EXMC

0

0

0

1

1

1

1

1

1

EXTI

16

16

16

16

16

16

16

16

16

ADC Unit (CHs)

2(16)

2(16)

2(16)

2(16)

2(16)

2(16)

2(21)

2(21)

2(21)

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP64

LQFP100

LQFP144

Memory map

Table 2-2. GD32F307xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

External device

 

 

AHB3

0xA000 0000 - 0xA000 0FFF

EXMC - SWREG

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC - NOR/PSRAM/SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB1

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

Reserved

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

Reserved

 

 

0x4002 6000 - 0x4002 63FF

Reserved

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

Reserved

 

 

0x4002 3C00 - 0x4002 3FFF

Reserved

 

 

0x4002 3800 - 0x4002 3BFF

Reserved

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2C00 - 0x4002 2FFF

Reserved

 

 

0x4002 2800 - 0x4002 2BFF

Reserved

 

 

0x4002 2400 - 0x4002 27FF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1C00 - 0x4002 1FFF

Reserved

 

 

0x4002 1800 - 0x4002 1BFF

Reserved

 

 

0x4002 1400 - 0x4002 17FF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0C00 - 0x4002 0FFF

Reserved

 

 

0x4002 0800 - 0x4002 0BFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA1

 

 

0x4002 0000 - 0x4002 03FF

DMA0

 

 

0x4001 8400 - 0x4001 FFFF

Reserved

 

 

0x4001 8000 - 0x4001 83FF

Reserved

 

 

APB2

0x4001 7C00 - 0x4001 7FFF

Reserved

 

 

0x4001 7800 - 0x4001 7BFF

Reserved

 

 

0x4001 7400 - 0x4001 77FF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 7000 - 0x4001 73FF

Reserved

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5C00 - 0x4001 67FF

Reserved

 

 

0x4001 5800 - 0x4001 5BFF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

TIMER10

 

 

0x4001 5000 - 0x4001 53FF

TIMER9

 

 

0x4001 4C00 - 0x4001 4FFF

TIMER8

 

 

0x4001 4800 - 0x4001 4BFF

Reserved

 

 

0x4001 4400 - 0x4001 47FF

Reserved

 

 

0x4001 4000 - 0x4001 43FF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

CTC

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 6000 - 0x4000 63FF

CAN SRAM 512 bytes

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

SRAM

 

 

 

AHB

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2006 0000 - 0x2006 FFFF

Reserved

 

 

0x2003 0000 - 0x2005 FFFF

Reserved

 

 

0x2001 8000 - 0x2002 FFFF

Reserved

 

 

0x2000 0000 - 0x2001 7FFF

SRAM

 

 

 

 

 

 

 

Code

 

 

 

 

 

 

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF F000 - 0x1FFF F7FF

 

 

Boot loader

 

 

0x1FFF C010 - 0x1FFF EFFF

 

 

 

0x1FFF C000 - 0x1FFF C00F

 

 

 

0x1FFF B000 - 0x1FFF BFFF

 

 

 

0x1FFF 7A10 - 0x1FFF AFFF

Reserved

 

 

0x1FFF 7800 - 0x1FFF 7A0F

Reserved

 

 

0x1FFF 0000 - 0x1FFF 77FF

Reserved

 

 

0x1FFE C010 - 0x1FFE FFFF

Reserved

 

 

0x1FFE C000 - 0x1FFE C00F

Reserved

 

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x1001 0000 - 0x1FFE BFFF

Reserved

0x1000 0000 - 0x1000 FFFF

Reserved

0x083C 0000 - 0x0FFF FFFF

Reserved

0x0830 0000 - 0x083B FFFF

Reserved

0x0810 0000 - 0x082F FFFF

Reserved

0x0800 0000 - 0x080F FFFF

Main Flash

0x0030 0000 - 0x07FF FFFF

Reserved

0x0010 0000 - 0x002F FFFF

 

Aliased to Main Flash or Boot loader

0x0002 0000 - 0x000F FFFF

0x0000 0000 - 0x0001 FFFF

 

GD32F307Zx LQFP144 pin definitions

Table 2-3. GD32F307Zx LQFP144 pin definitions

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4

Alternate:TRACED1, EXMC_A20

 

PE5

 

4

 

I/O

 

5VT

Default: PE5 Alternate:TRACED2, EXMC_A21

Remap: TIMER8_CH0(3)

 

PE6

 

5

 

I/O

 

5VT

Default: PE6 Alternate:TRACED3, EXMC_A22

Remap: TIMER8_CH1(3)

VBAT

6

P

 

Default: VBAT

PC13- TAMPER- RTC

 

7

 

I/O

 

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

 

8

 

I/O

 

Default: PC14 Alternate: OSC32IN

PC15-

OSC32OUT

 

9

 

I/O

 

Default: PC15 Alternate: OSC32OUT

 

PF0

 

10

 

I/O

 

5VT

Default: PF0 Alternate: EXMC_A0

Remap: CTC_SYNC

 

PF1

 

11

 

I/O

 

5VT

Default: PF1 Alternate: EXMC_A1

 

PF2

 

12

 

I/O

 

5VT

Default: PF2

Alternate: EXMC_A2

 

PF3

 

13

 

I/O

 

5VT

Default: PF3 Alternate: EXMC_A3

 

PF4

 

14

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4

 

PF5

 

15

 

I/O

 

5VT

Default: PF5 Alternate: EXMC_A5

VSS_5

16

P

 

Default: VSS_5

VDD_5

17

P

 

Default: VDD_5

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Default: PF6

PF6

18

I/O

 

Alternate: EXMC_NIORD

 

 

 

 

Remap: TIMER9_CH0

 

 

 

 

Default: PF7

PF7

19

I/O

 

Alternate: EXMC_NREG

 

 

 

 

Remap: TIMER10_CH0(3)

 

 

 

 

Default: PF8

PF8

20

I/O

 

Alternate: EXMC_NIOWR

 

 

 

 

Remap: TIMER12_CH0(3)

 

 

 

 

Default: PF9

PF9

21

I/O

 

Alternate: EXMC_CD

 

 

 

 

Remap: TIMER13_CH0(3)

 

PF10

 

22

 

I/O

 

Default: PF10

Alternate: EXMC_INTR

 

OSCIN

 

23

 

I

 

Default: OSCIN

Remap: PD0

 

OSCOUT

 

24

 

O

 

Default: OSCOUT

Remap: PD1

NRST

25

I/O

 

Default: NRST

 

PC0

 

26

 

I/O

 

Default: PC0

Alternate: ADC01_IN10

 

PC1

 

27

 

I/O

 

Default: PC1

Alternate: ADC01_IN11, ENET_MDC

 

PC2

 

28

 

I/O

 

Default: PC2

Alternate: ADC01_IN12, ENET_MII_TXD2

 

PC3

 

29

 

I/O

 

Default: PC3

Alternate: ADC01_IN13, ENET_MII_TX_CLK

VSSA

30

P

 

Default: VSSA

VREF-

31

P

 

Default: VREF-

VREF+

32

P

 

Default: VREF+

VDDA

33

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

34

I/O

 

Alternate: WKUP, USART1_CTS, ADC01_IN0,

TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,

 

 

 

 

TIMER7_ETI, ENET_MII_CRS

 

 

 

 

Default: PA1

PA1

35

I/O

 

Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1,

TIMER4_CH1, ENET_MII_RX_CLK,

 

 

 

 

ENET_RMII_REF_CLK

 

 

 

 

Default: PA2

PA2

36

I/O

 

Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,

 

 

 

 

TIMER4_CH2, TIMER8_CH0(3), ENET_MDIO,

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

SPI0_IO2

 

 

 

 

Default: PA3

PA3

37

I/O

 

Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3,

TIMER4_CH3, TIMER8_CH1(3), ENET_MII_COL,

 

 

 

 

SPI0_IO3

VSS_4

38

P

 

Default: VSS_4

VDD_4

39

P

 

Default: VDD_4

 

 

 

 

Default: PA4

PA4

40

I/O

 

Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,

DAC_OUT0

 

 

 

 

Remap:SPI2_NSS, I2S2_WS

 

PA5

 

41

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

 

 

 

 

Default: PA6

PA6

42

I/O

 

Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,

TIMER7_BRKIN, TIMER12_CH0(3)

 

 

 

 

Remap: TIMER0_BRKIN

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,

PA7

43

I/O

 

TIMER7_CH0_ON, TIMER13_CH0(3),

 

 

 

 

ENET_MII_RX_DV, ENET_RMII_CRS_DV

 

 

 

 

Remap: TIMER0_CH0_ON

 

 

 

 

Default: PC4

PC4

44

I/O

 

Alternate: ADC01_IN14, ENET_MII_RXD0,

 

 

 

 

ENET_RMII_RXD0

 

 

 

 

Default: PC5

PC5

45

I/O

 

Alternate: ADC01_IN15, ENET_MII_RXD1,

 

 

 

 

ENET_RMII_RXD1

 

 

 

 

Default: PB0

PB0

46

I/O

 

Alternate: ADC01_IN8, TIMER2_CH2,

TIMER7_CH1_ON, ENET_MII_RXD2

 

 

 

 

Remap: TIMER0_CH1_ON

 

 

 

 

Default: PB1

PB1

47

I/O

 

Alternate: ADC01_IN9, TIMER2_CH3,

TIMER7_CH2_ON, ENET_MII_RXD3

 

 

 

 

Remap: TIMER0_CH2_ON

PB2

48

I/O

5VT

Default: PB2, BOOT1

 

PF11

 

49

 

I/O

 

5VT

Default: PF11

Alternate: EXMC_NIOS16

 

PF12

 

50

 

I/O

 

5VT

Default: PF12

Alternate: EXMC_A6

VSS_6

51

P

 

Default: VSS_6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VDD_6

52

P

 

Default: VDD_6

 

PF13

 

53

 

I/O

 

5VT

Default: PF13

Alternate: EXMC_A7

 

PF14

 

54

 

I/O

 

5VT

Default: PF14 Alternate: EXMC_A8

 

PF15

 

55

 

I/O

 

5VT

Default: PF15

Alternate: EXMC_A9

 

PG0

 

56

 

I/O

 

5VT

Default: PG0 Alternate: EXMC_A10

 

PG1

 

57

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11

 

PE7

 

58

 

I/O

 

5VT

Default: PE7 Alternate: EXMC_D4

Remap: TIMER0_ETI

 

PE8

 

59

 

I/O

 

5VT

Default: PE8 Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

 

PE9

 

60

 

I/O

 

5VT

Default: PE9

Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

61

P

 

Default: VSS_7

VDD_7

62

P

 

Default: VDD_7

 

PE10

 

63

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

PE11

 

64

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8

Remap: TIMER0_CH1

 

PE12

 

65

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

 

PE13

 

66

 

I/O

 

5VT

Default: PE13

Alternate: EXMC_D10 Remap: TIMER0_CH2

 

PE14

 

67

 

I/O

 

5VT

Default: PE14

Alternate: EXMC_D11 Remap: TIMER0_CH3

 

PE15

 

68

 

I/O

 

5VT

Default: PE15 Alternate: EXMC_D12

Remap: TIMER0_BRKIN

 

PB10

 

69

 

I/O

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX, ENET_MII_RX_ER

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: TIMER1_CH2

 

 

PB11

 

 

70

 

 

I/O

 

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX, ENET_MII_TX_EN, ENET_RMII_TX_EN

Remap: TIMER1_CH3

VSS_1

71

P

 

Default: VSS_1

VDD_1

72

P

 

Default: VDD_1

 

 

PB12

 

 

73

 

 

I/O

 

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS, CAN1_RX,

ENET_MII_TXD0, ENET_RMII_TXD0

 

 

PB13

 

 

74

 

 

I/O

 

 

5VT

Default: PB13

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX, ENET_MII_TXD1, ENET_RMII_TXD1

 

PB14

 

75

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0(3)

 

PB15

 

76

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1(3)

 

 

PD8

 

 

77

 

 

I/O

 

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX, ENET_MII_RX_DV,

ENET_RMII_CRS_DV

 

 

PD9

 

 

78

 

 

I/O

 

 

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX, ENET_MII_RXD0,

ENET_RMII_RXD0

 

 

PD10

 

 

79

 

 

I/O

 

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, ENET_MII_RXD1,

ENET_RMII_RXD1

 

PD11

 

80

 

I/O

 

5VT

Default: PD11 Alternate: EXMC_A16

Remap: USART2_CTS, ENET_MII_RXD2

 

 

PD12

 

 

81

 

 

I/O

 

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS,

ENET_MII_RXD3

 

PD13

 

82

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18

Remap: TIMER3_CH1

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VSS_8

83

P

 

Default: VSS_8

VDD_8

84

P

 

Default: VDD_8

 

PD14

 

85

 

I/O

 

5VT

Default: PD14

Alternate: EXMC_D0 Remap: TIMER3_CH2

 

PD15

 

86

 

I/O

 

5VT

Default: PD15 Alternate: EXMC_D1

Remap: TIMER3_CH3, CTC_SYNC

 

PG2

 

87

 

I/O

 

5VT

Default: PG2 Alternate: EXMC_A12

 

PG3

 

88

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13

 

PG4

 

89

 

I/O

 

5VT

Default: PG4 Alternate: EXMC_A14

 

PG5

 

90

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15

 

PG6

 

91

 

I/O

 

5VT

Default: PG6 Alternate: EXMC_INT1

 

PG7

 

92

 

I/O

 

5VT

Default: PG7

Alternate: EXMC_INT2

PG8

93

I/O

5VT

Default: PG8

VSS_9

94

P

 

Default: VSS_9

VDD_9

95

P

 

Default: VDD_9

 

PC6

 

96

 

I/O

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

 

PC7

 

97

 

I/O

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

 

PC8

 

98

 

I/O

 

5VT

Default: PC8

Alternate: TIMER7_CH2 Remap: TIMER2_CH2

 

PC9

 

99

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

 

PA8

 

100

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF, CTC_SYNC

 

PA9

 

101

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

PA10

102

I/O

5VT

Default: PA10

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

 

PA11

 

103

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

 

PA12

 

104

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

 

PA13

 

105

 

I/O

 

5VT

Default: JTMS, SWDIO

Remap: PA13

NC

106

-

-

-

VSS_2

107

P

 

Default: VSS_2

VDD_2

108

P

 

Default: VDD_2

 

PA14

 

109

 

I/O

 

5VT

Default: JTCK, SWCLK

Remap: PA14

 

 

PA15

 

 

110

 

 

I/O

 

 

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

111

 

I/O

 

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

 

PC11

 

112

 

I/O

 

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

 

PC12

 

113

 

I/O

 

5VT

Default: PC12 Alternate: UART4_TX

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

114

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2

Remap: CAN0_RX, OSCIN

 

PD1

 

115

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX, OSCOUT

 

PD2

 

116

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

 

PD3

 

117

 

I/O

 

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS

 

PD4

 

118

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

119

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: USART1_TX

VSS_10

120

P

 

Default: VSS_10

VDD_10

121

P

 

Default: VDD_10

 

PD6

 

122

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT Remap: USART1_RX

 

PD7

 

123

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

124

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2

 

PG10

 

125

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2

 

PG11

 

126

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1

 

PG12

 

127

 

I/O

 

5VT

Default: PG12

Alternate: EXMC_NE3

 

PG13

 

128

 

I/O

 

5VT

Default: PG13

Alternate: EXMC_A24

 

PG14

 

129

 

I/O

 

5VT

Default: PG14

Alternate: EXMC_A25

VSS_11

130

P

 

Default: VSS_11

VDD_11

131

P

 

Default: VDD_11

PG15

132

I/O

5VT

Default: PG15

 

 

PB3

 

 

133

 

 

I/O

 

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1,

SPI0_SCK

 

PB4

 

134

 

I/O

 

5VT

Default: NJTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

 

PB5

 

 

135

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD, ENET_MII_PPS_OUT, ENET_RMII_PPS_OUT

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

 

PB6

 

136

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX, SPI0_IO2

 

PB7

 

137

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX, SPI0_IO3

BOOT0

138

I

 

Default: BOOT0

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

PB8

 

 

139

 

 

I/O

 

 

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0(3), ENET_MII_TXD3

Remap: I2C0_SCL, CAN0_RX

 

PB9

 

140

 

I/O

 

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0(3) Remap: I2C0_SDA, CAN0_TX

 

PE0

 

141

 

I/O

 

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0

 

PE1

 

142

 

I/O

 

5VT

Default: PE1

Alternate: EXMC_NBL1

VSS_3

143

P

 

Default: VSS_3

VDD_3

144

P

 

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power. 
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available in GD32F307ZG devices.

3.1.ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
Floating Point Unit (FPU)


3.2.On-chip memory

Up to 1024 Kbytes of Flash memory, including code Flash and data Flash
96 KB of SRAM

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner flash at most, which includes code Flash that available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. An extra data Flash is also included for storing data mainly. Table 2-2. GD32F307xx memory map shows the memory of the GD32F307xx

series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.


Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 120 MHz The maximum frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz See Figure 2-5 GD32F307xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6) and USBFS (PA9, PA11 and PA12) is also available for boot functions. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default

condition, boot from bank0 of Flash memory is selected. It also supports to boot from bank1 of Flash memory by setting a bit in option bytes.

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, the USB wakeup and ENET wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.6 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to two 12-bit 2.6 MSPS multi-channel ADCs are integrated in the device. It has a total of 18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), and 1 channel for internal reference voltage (VREFINT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.

The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

Two 12-bit DACs with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller

The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.

3.8.DMA

7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 112 general purpose I/O pins (GPIO) in GD32F307xx, named PA0 ~ PA15 and  PB0  ~ PB15,  PC0  ~  PC15,  PD0  ~ PD15,  PE0  ~  PE15,  PF0-PF15,  PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-

up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge-aligned or center-aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 ~ TIMER4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~ TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F307xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in

debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wakeup event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides several data transfer rates of up to 100 KHz in standard mode, up to 400 KHz in fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode

Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI0.

Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 7.5M Bits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication except UART4.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F307xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.

Universal serial bus full-speed interface (USBFS)

One USB device/host/full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator (IRC48M) support crystal-less operation
Internal main PLL for USBCLK compliantly
Internal USBFS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator (IRC48M) in automatic trimming mode that allows crystal-less operation.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Ethernet (ENET)

IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 16 with 25 MHz output and RMII up to 7 with 50 MHz output. The function of 32-bit CRC checking is also available.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and PC card
Provide ECC calculating hardware module for NAND Flash memory block
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and PC card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F307Zx), LQFP100 (GD32F307Vx) and LQFP64 (GD32F307Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗,指纹门锁并不是什么新鲜事,我相信每个人都很熟悉。随着近年来智能家居的逐步普及,指纹门锁也进入了成千上万的家庭。今天的功耗雷达模块指纹门锁不仅消除了繁琐的钥匙,而且还提供了各种智能功能,uA级别智能门锁低功耗雷达模块用在智能门锁上,可以实现门锁的智能感应屏幕,使电池寿命延长3-5倍,如与其他智能家居连接,成为智能场景的开关。所以今天的指纹门锁更被称为智能门锁。 今天,让我们来谈谈功耗雷达模块智能门锁的安全性。希望能让更多想知道智能门锁的朋友认识下。 指纹识别是智能门锁的核心 指纹识别技术在我们的智能手机上随处可见。从以前的实体指纹识别到屏幕下的指纹识别,可以说指纹识别技术已经相当成熟。指纹识别可以说是整个uA级低功耗雷达模块智能门锁的核心。 目前主要有三种常见的指纹识别方法,即光学指纹识别、半导体指纹识别和超声指纹识别。 光学指纹识别 让我们先谈谈光学指纹识别的原理实际上是光的反射。我们都知道指纹本身是不均匀的。当光照射到我们的指纹上时,它会反射,光接收器可以通过接收反射的光来绘制我们的指纹。就像激光雷达测绘一样。 光学指纹识别通常出现在打卡机上,手机上的屏幕指纹识别技术也使用光学指纹识别。今天的光学指纹识别已经达到了非常快的识别速度。 然而,光学指纹识别有一个缺点,即硬件上的活体识别无法实现,容易被指模破解。通常,活体识别是通过软件算法进行的。如果算法处理不当,很容易翻车。 此外,光学指纹识别也容易受到液体的影响,湿手解锁的成功率也会下降。 超声指纹识别 超声指纹识别也被称为射频指纹识别,其原理与光学类型相似,但超声波使用声波反射,实际上是声纳的缩小版本。因为使用声波,不要担心水折射会降低识别率,所以超声指纹识别可以湿手解锁。然而,超声指纹识别在防破解方面与光学类型一样,不能实现硬件,可以被指模破解,活体识别仍然依赖于算法。 半导体指纹识别 半导体指纹识别主要采用电容、电场(即我们所说的电感)、温度和压力原理来实现指纹图像的收集。当用户将手指放在前面时,皮肤形成电容阵列的极板,电容阵列的背面是绝缘极板。由于不同区域指纹的脊柱与谷物之间的距离也不同,因此每个单元的电容量随之变化,从而获得指纹图像。半导体指纹识别具有价格低、体积小、识别率高的优点,因此大多数uA级低功耗雷达模块智能门锁都采用了这种方案。半导体指纹识别的另一个功能是活体识别。传统的硅胶指模无法破解。 当然,这并不意味着半导体可以百分识别活体。所谓的半导体指纹识别活体检测不使用指纹活体体征。本质上,它取决于皮肤的材料特性,这意味着虽然传统的硅胶指模无法破解。 一般来说,无论哪种指纹识别,都有可能被破解,只是说破解的水平。然而,今天的指纹识别,无论是硬件生活识别还是算法生活识别,都相对成熟,很难破解。毕竟,都可以通过支付级别的认证,大大保证安全。 目前,市场上大多数智能门锁仍将保留钥匙孔。除了指纹解锁外,用户还可以用传统钥匙开门。留下钥匙孔的主要目的是在指纹识别故障或智能门锁耗尽时仍有开门的方法。但由于有钥匙孔,它表明它可以通过技术手段解锁。 目前市场上的锁等级可分为A、B、C三个等级,这三个等级主要是通过防暴开锁和防技术开锁的程度来区分的。A级锁要求技术解锁时间不少于1分钟,B级锁要求不少于5分钟。即使是高级别的C级锁也只要求技术解锁时间不少于10分钟。 也就是说,现在市场上大多数门锁,无论是什么级别,在专业的解锁大师面前都糊,只不过是时间长短。 安全是重要的,是否安全增加了人们对uA级别低功耗雷达模块智能门锁安全的担忧。事实上,现在到处都是摄像头,强大的人脸识别,以及移动支付的出现,使家庭现金减少,所有这些都使得入室盗窃的成本急剧上升,近年来各省市的入室盗窃几乎呈悬崖状下降。 换句话说,无论锁有多安全,无论锁有多难打开,都可能比在门口安装摄像头更具威慑力。 因此,担心uA级别低功耗雷达模块智能门锁是否不安全可能意义不大。毕竟,家里的防盗锁可能不安全。我们应该更加关注门锁能给我们带来多少便利。 我们要考虑的是智能门锁的兼容性和通用性。毕竟,智能门锁近年来才流行起来。大多数人在后期将普通机械门锁升级为智能门锁。因此,智能门锁能否与原门兼容是非常重要的。如果不兼容,发现无法安装是一件非常麻烦的事情。 uA级别低功耗雷达模块智能门锁主要是为了避免带钥匙的麻烦。因此,智能门锁的便利性尤为重要。便利性主要体现在指纹的识别率上。手指受伤导致指纹磨损或老年人指纹较浅。智能门锁能否识别是非常重要的。 当然,如果指纹真的失效,是否有其他解锁方案,如密码解锁或NFC解锁。还需要注意密码解锁是否有虚假密码等防窥镜措施。 当然,智能门锁的耐久性也是一个需要特别注意的地方。uA级别低功耗雷达模块智能门锁主要依靠内部电池供电,这就要求智能门锁的耐久性尽可能好,否则经常充电或更换电池会非常麻烦。
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发布时间: : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用,如今,家用电器的智能化已成为一种常态,越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入,今天就来说说这个话题。 什么是智能浴室镜?智慧型浴室镜,顾名思义,就是卫浴镜子智能化升级,入门级产品基本具备了彩灯和镜面触摸功能,更高档次的产品安装有微波雷达传感器智能感应,当感应到有人接近到一定距离即可开启亮灯或者亮屏操作,也可三色无极调,智能除雾,语音交互,日程安排备忘,甚至在镜子上看电视,听音乐,气象预报,问题查询,智能控制,健康管理等。 智能化雷达感应浴室镜与普通镜的区别,为什么要选TA?,就功能而言,普通浴镜价格用它没有什么压力!而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言,普通浴镜功能单一,而微波雷达传感器智能浴室镜功能创新:镜子灯光色温和亮度可以自由调节,镜面还可以湿手触控,智能除雾,既环保又健康! 尽管智能浴镜比较新颖,但功能丰富,体验感更好,特别是入门级的智能浴镜,具有基础智能化功能,真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么? ①确定智能浴室镜的安装位置,因为是安装时在墙壁上打孔,一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时,根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后,在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度,一般智能浴镜的标准安装高度约85cm(从地砖到镜子底),具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍,可用酒精或30%清洁稀释液擦洗,平时可用干毛巾养护,注意多通风。
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发布时间: : 2022-02--07
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31
2023-01

上海乐鑫科技官网ESP32 ble wifi模块数据安全性揭秘

发布时间: : 2023-01--31
上海乐鑫科技官网ESP32 ble wifi模块数据安全性揭秘,众所周知,TCP 协议和 UDP 协议,及其之上的应用协议 HTTP 和 COAP,都是明文传输数据的,这样就会导致数据在网络传输的过程中被窃取或者篡改。如果数据中含有密码、账号等敏感信息,则可能会造成不可挽回的损失,因此需要对这些明文传输的数据进行加密。对于使用蓝牙传输的数据,由于蓝牙协议属于点对点的协议,数据不会泄露到网络上,被窃取的概率也很小;另外,上海乐鑫科技官网ESP32 ble wifi模块蓝牙协议本身也会对用户的数据进行加密。因此,本文主要讨论 TCP IP协议的数据加密。 加密是为了保证传输数据的机密性与完整性。常见的加密系统通常先对数据进行编码再传输例如,在以前的战争中,发送的电报就是经过编码的,接收方和发送方都有一个相同的密码本,接收方用密码本上的数字或者字母来替换电报中的单词、语句。即使电报内容被第三窃听了,第三方也无法在短时间破译出电报的真实内容。但是这种方式有个缺陷,就是电报的内容还是存在被破解的可能,只是时间的问题,而且为了防止电报被破解,接收方与发送方需要定期更换密码本,这时也有可能泄露密码本,导致电报内容被破解。 上述的电报例子就是常见的加密算法——对称加密的使用场景。在对称加密算法中,加密与解密采用的算法是一样的,它们的密钥也都是一样的。对称加密具有算法公开、计算量小、加密速度快、加密效率高等优点。但在数据传输前,发送方和接收方必须商定好密钥,而目为了保证数据不被破解,双方还必须定期更新密钥,这会使得密钥管理成为双方的负担。常用的对称加密算法有 AES、DES、RC4 等。 接下来介绍与对称加密相对的算法——非对称加密。上海乐鑫科技官网ESP32 ble wifi模块非对称加密的双方都有一对公开密钥(Public Key,公钥)与私有密钥 (Private Key,私钥),数据的加密使用公钥进行,数据的解密使用私钥进行。因为加密和解密使用的是两个不同的密钥,所以这种加密算法称为非对称加密。相比于对称加密,非对称加密更加安全。因为非对称加密比对称加密更复杂,所以在解密时会比对称加密慢,而且第三方很难直接破译数据。因为非对称加密算法的复杂度很高,并且用于解密的私钥是不会在网络中传播的,只有接收方才能获取到私钥,所以大大提高了数据的安全性。常见的非对称加密算法有 RSA、Diffe-Hellman、DSA等。 上海乐鑫科技官网ESP32 ble wifi模块非对称加密的优点是其安全性,用户 A 可以保留私钥,通过网络将公传输给用户 B,即使用户C获取了公钥,因为用户 C 没有用户A 的私钥,用户C 也是无法破解数据内容的。这样用户A 和用户B 就可以大胆地通过网络传输各自的公钥。记住一点,公钥是用于加密的,私钥是用于解密的。 非对称加密看起来似乎很安全,但是有没有想过这样一个问题: 如果用户C 将发往用户A 和用户 B 的公钥全部替换为自己对应私钥的公呢?用户 A 是不知道这个公是不是用户 B的,所以当用户A 发送数据时,就会使用用户 C 的公钥进行加密,这时用户 C 就可以在窃取该密文数据后使用对应的私钥进行解密。因此,如何保证公钥的合法性是至关重要的。在现实中,通过 CA (Certificate Authority) 可以保证公的合法性。CA 也是基于非对称加密算法来工作的,有了 CA,用户 B 会先把自己的公钥和一些其他信息交给 CA,CA 用自己的私钥加密这些数据,加密完的数据称为用户 B 的数字证书。用户 B 向用户A 传输的公是CA加密之后的数字证书。用户A 收到数宁证书后,会通过 CA 发布的数字证书 (包含了 CA的公钥)来解密用户B的数字证书,从而获得用户B 的公钥。
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30
2023-01

乐鑫科技ESP32-C3蓝牙WiFi模块数据通信协议总结TCP/UDP/HTTP/CoAP协议

发布时间: : 2023-01--30
乐鑫科技ESP32-C3蓝牙WiFi模块数据通信协议总结TCP/UDP/HTTP/CoAP协议 乐鑫科技ESP32-C3蓝牙WiFi模块TCP 协议 可靠传输,支持重传、流量控制和拥塞控制; 面向连接,通过 3 次握手建立连接和 4 次握手断开连接,长连接; 一对一连接; 包头小为 20 B; 根据网络环境,在出现丢包时会重传,导致传输速率降低; 适用于可靠传输的应用,如文件传输等; 乐鑫科技ESP32-C3蓝牙WiFi模块UDP 协议 不可靠传输,不支持重传、流量控制和拥塞控制; 无连接,直接进行数据传输,短连接; 支持一对一单播,一对所有的广播和一对多的组播; 包头只有8B; 快,不受网络环境影响,只负责将数据传输到网络; 适用于实时传输应用,如 VoIP 电话、视频电话、流媒体等; 对于本地控制的数据通信而言,单纯从传输层的角度来讲,可选择 TCP 协议,因为需要数据的准确性;在使用 UDP 协议时,智能手机 App 会发送开灯命令,可能该命令由于网络环境问题被丢弃了,ESP32-C3 可能就无法收到该命令;相比于 TCP 协议而言,就算数据包被丢弃了,智能手机 App 底层还会重新发送该命令。 但使用单纯的传输层协议发送数据有个缺陷,需要用户自行开发上层应用业务逻辑,所以本节又介绍了基于 TCP和UDP 协议的应用协议 HTTP 和 COAP。 HTTP和CoAP 都是基于 REST 模型的网络传输协议,用于发送请求与响应请求,只是它们-个基于 TCP 协议,另一个基于 UDP 协议,并且各自继承了传输层协议的相关特性。HTTP 协议和 CoAP 协议的区别如下表所示。 乐鑫科技ESP32-C3蓝牙WiFi模块HTTP 协议 传输层TCP 协议; 可能含有大量消息头数据,开销大; 长连接,功耗高; 资源发现不支持; 一般由客户端主动触发,服务器端无法主动触发; 适用于性能好、内存比较多的设备; 乐鑫科技ESP32-C3蓝牙WiFi模块CoAP 协议 传输层UDP 协议; 包头采用二进制压缩,开销小; 短连接,功耗低; 资源发现支持; 虽然也有客户端与服务器端之分,但两者都可以主动触发; 适用于性能差、内存比较少的设备; 相比较而言,CoAP 协议更适合一些资源少的物联网设备,如果设备资源多、性能好,HTTP协议的功能比 CoAP 协议更加健全。对比了 TCP/IP 协议族内的通信协议后,接下来比较该类协议与蓝牙协议,它们直观的区别就是,蓝牙是点对点的协议,而 TCP/IP 协议是端对端的协议,中间可能会经过路由。因此在速度响应方面,同样是 2.4 GHZ 频道的无线传输技术,智能手机到 ESP32-C3 之间的数据通信上,蓝牙要快于 Wi-Fi。乐鑫科技ESP32-C3蓝牙WiFi模块蓝牙的数据包大小会比使用TCP/IP 协议栈的应用数据更小;蓝牙的功耗天然地比 Wi-Fi 功耗低。蓝牙协议支持资源发现,也不需要本地发现,因为蓝牙是点对点的连接,可以说蓝牙非常适合用于本地控制。但由于目前大部分物联网产品都要连云所以 Wi-Fi功能是必不可少的。很多物联网产品都可以只使用 Wi-Fi或者只使用蓝牙进行配网如果物联网产品不需要连云,则可以只使用蓝牙进行本地控制;如果物联网产品需要连云,则需要借助 Wi-Fi连云和进行本地控制。
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29
2023-01

飞睿科技代理商乐鑫WiFi6 Soc ESP32-C6现货ESP-IDF v5.0发布

发布时间: : 2023-01--29
飞睿科技代理商乐鑫WiFi6 Soc ESP32-C6现货ESP-IDF v5.0发布,ESP32-C6是乐鑫科技的支持WiFi6的SoC,集成2.4GHz Wi-Fi6、Bluetooth5(LE)和IEEE802.15.4协议(Thread/Zigbee)。目前,ESP32-C6已上架销售,可到飞睿科技官方淘宝店购买。 飞睿科技代理商乐鑫ESP32-C6 一个时钟频率高达1600MHz的高性能RISC-V32位处理器,一个时钟频率高20位MHz的低功耗RISC-V内置512位处理器的32位处理器KBSRAM,320KBROM,并支持外接flash。ESP32-C6拥有30个(QFN40)或22个(QFN32)可编程GPIO管脚,支持SPI.UART.I2C.I2S.RMT.TWAI.PWM.电机控制PWM和SDIO。它还集成了12位ADC和温度传感器。 ESP32-C6支持Matter,可用于构建MatteroverWi-Fi终端设备和MatteroverThread实现多系统终端设备,实现多系统.多平台智能家居设备的无缝通信与合作。还可用于构建Thread边界路由器等其他Matter解决方案.Matter网关和Zigbee网桥。 飞睿科技代理商ESP32-C6由乐鑫成熟的物联网开发框架组成ESP-IDF提供软件支持。目前正在开发中的。ESP-IDFv5.1将包含对ESP32-C6的初步支持。ESP-IDF对ESP32-C6的功能支持列表。用户通过乐心ESP-AT和ESP-HostedSDK,可将ESP32-C6用作外部主机的协处理器。ESP32-C66还支持乐信构建AIOT产品的完整云平台方案 ESPRainMaker®。 如您对ESP32-C6系列产品感兴趣,请联系我们的客户支持团队。 乐鑫近期发布了 ESP-IDFv5.0,对ESP-IDFv4.x重大更新,这是目前新的稳定版。v5.0版本可以和大多数一起使用v4.x版本构建的应用程序兼容性也进行了一些非兼容性更新,并删除了一些废弃的功能。用户在更新项目时需要相应地修改代码。 ESP-IDFv5.0的新特征包括: 支持:ESP32-C2和ESP32-H2SoC;对其他ESP32SoC(ESP32-S2.ESP32-S3和ESP32-C3)扩展支持;安全功能包括OTA升级期间预加密固件的分发、更安全的Wi-Fi新增配网系统Wi-Fi支持快速Station切换的802.11r,SoftAP在Station模式下进行WPS注册和WPS注册WPA3SAEH2E。 v5.0版本还进行了一系列的bug修复,比如ESP32-C3和ESP32-S3部件上的电子保险丝问题,使用RTC时的上电复位问题,降低了一些应用的功耗,修复了ESP32-S3睡眠模式下的某些电源参数。 然而,当你将项目从旧版本迁移到ESP-IDFv5.0点,还需要仔细考虑新版本的一系列非兼容性更新,如更新蓝牙操作的应用程序编程界面(API)、构建系统、网络(包括从OpenSSL到mbedTLS或esp-tls加密),删除旧的ADC驱动程序,不再对Python3.6提供支持。 目前正在开发中ESP-IDFv5.1将包含对飞睿科技代理商乐鑫ESP32-C6 初步支持。
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