这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F307VGT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F307VGT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F307xx ARM® Cortex®-M4 32-bit MCU Datasheet General description The GD32F307xx device belongs to the mainstream line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F307xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1024 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 2.6 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss, two CANs, a USBFS and an ENET. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make GD32F307xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, communication networks, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, IoT and so on. Device information Table 2-1. GD32F307xx devices features and peripheral list   Part Number GD32F307xx   RC RE RG VC VE VG ZC ZE ZG Flash Code area (KB)   256   256   256   256   256   256   256   256   256   Data area (KB)   0   256   768   0   256   768   0   256   768   Total (KB) 256 512 1024 256 512 1024 256 512 1024 SRAM (KB) 96 96 96 96 96 96 96 96 96 Timers General timer(16-bit) 4 (1-4) 4 (1-4) 10 (1-4,8-13) 4 (1-4) 4 (1-4) 10 (1-4,8-13) 4 (1-4) 4 (1-4) 10 (1-4,8-13)   Advanced timer(16-bit) 1 (0) 2 (0,7) 2 (0,7) 1 (0) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7)   Basic timer(16-bit) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6) 2 (5-6)   SysTick 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 1 Connectivity   USART 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2) 3 (0-2)     UART 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4)   I2C 2 2 2
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F307VGT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F307xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

General description

The GD32F307xx device belongs to the mainstream line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support.
The GD32F307xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1024 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 2.6 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss, two CANs, a USBFS and an ENET.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make GD32F307xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, communication networks, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, IoT and so on.

Device information

Table 2-1. GD32F307xx devices features and peripheral list

 

Part Number

GD32F307xx

 

RC

RE

RG

VC

VE

VG

ZC

ZE

ZG

Flash

Code area

(KB)

 

256

 

256

 

256

 

256

 

256

 

256

 

256

 

256

 

256

 

Data area

(KB)

 

0

 

256

 

768

 

0

 

256

 

768

 

0

 

256

 

768

 

Total (KB)

256

512

1024

256

512

1024

256

512

1024

SRAM (KB)

96

96

96

96

96

96

96

96

96

Timers

General

timer(16-bit)

4

(1-4)

4

(1-4)

10

(1-4,8-13)

4

(1-4)

4

(1-4)

10

(1-4,8-13)

4

(1-4)

4

(1-4)

10

(1-4,8-13)

 

Advanced

timer(16-bit)

1

(0)

2

(0,7)

2

(0,7)

1

(0)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

Basic

timer(16-bit)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

2

(5-6)

 

SysTick

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

 

USART

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

3

(0-2)

 

 

UART

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

 

I2C

2

2

2

2

2

2

2

2

2

 

 

SPI/I2S

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

 

ENET

1

1

1

1

1

1

1

1

1

 

CAN

2

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

1

GPIO

51

51

51

80

80

80

112

112

112

EXMC

0

0

0

1

1

1

1

1

1

EXTI

16

16

16

16

16

16

16

16

16

ADC Unit (CHs)

2(16)

2(16)

2(16)

2(16)

2(16)

2(16)

2(21)

2(21)

2(21)

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP64

LQFP100

LQFP144

Memory map

Table 2-2. GD32F307xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

External device

 

 

AHB3

0xA000 0000 - 0xA000 0FFF

EXMC - SWREG

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC - NOR/PSRAM/SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB1

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

Reserved

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

Reserved

 

 

0x4002 6000 - 0x4002 63FF

Reserved

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

Reserved

 

 

0x4002 3C00 - 0x4002 3FFF

Reserved

 

 

0x4002 3800 - 0x4002 3BFF

Reserved

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2C00 - 0x4002 2FFF

Reserved

 

 

0x4002 2800 - 0x4002 2BFF

Reserved

 

 

0x4002 2400 - 0x4002 27FF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1C00 - 0x4002 1FFF

Reserved

 

 

0x4002 1800 - 0x4002 1BFF

Reserved

 

 

0x4002 1400 - 0x4002 17FF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0C00 - 0x4002 0FFF

Reserved

 

 

0x4002 0800 - 0x4002 0BFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA1

 

 

0x4002 0000 - 0x4002 03FF

DMA0

 

 

0x4001 8400 - 0x4001 FFFF

Reserved

 

 

0x4001 8000 - 0x4001 83FF

Reserved

 

 

APB2

0x4001 7C00 - 0x4001 7FFF

Reserved

 

 

0x4001 7800 - 0x4001 7BFF

Reserved

 

 

0x4001 7400 - 0x4001 77FF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 7000 - 0x4001 73FF

Reserved

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5C00 - 0x4001 67FF

Reserved

 

 

0x4001 5800 - 0x4001 5BFF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

TIMER10

 

 

0x4001 5000 - 0x4001 53FF

TIMER9

 

 

0x4001 4C00 - 0x4001 4FFF

TIMER8

 

 

0x4001 4800 - 0x4001 4BFF

Reserved

 

 

0x4001 4400 - 0x4001 47FF

Reserved

 

 

0x4001 4000 - 0x4001 43FF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

CTC

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 6000 - 0x4000 63FF

CAN SRAM 512 bytes

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

SRAM

 

 

 

AHB

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2006 0000 - 0x2006 FFFF

Reserved

 

 

0x2003 0000 - 0x2005 FFFF

Reserved

 

 

0x2001 8000 - 0x2002 FFFF

Reserved

 

 

0x2000 0000 - 0x2001 7FFF

SRAM

 

 

 

 

 

 

 

Code

 

 

 

 

 

 

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF F000 - 0x1FFF F7FF

 

 

Boot loader

 

 

0x1FFF C010 - 0x1FFF EFFF

 

 

 

0x1FFF C000 - 0x1FFF C00F

 

 

 

0x1FFF B000 - 0x1FFF BFFF

 

 

 

0x1FFF 7A10 - 0x1FFF AFFF

Reserved

 

 

0x1FFF 7800 - 0x1FFF 7A0F

Reserved

 

 

0x1FFF 0000 - 0x1FFF 77FF

Reserved

 

 

0x1FFE C010 - 0x1FFE FFFF

Reserved

 

 

0x1FFE C000 - 0x1FFE C00F

Reserved

 

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x1001 0000 - 0x1FFE BFFF

Reserved

0x1000 0000 - 0x1000 FFFF

Reserved

0x083C 0000 - 0x0FFF FFFF

Reserved

0x0830 0000 - 0x083B FFFF

Reserved

0x0810 0000 - 0x082F FFFF

Reserved

0x0800 0000 - 0x080F FFFF

Main Flash

0x0030 0000 - 0x07FF FFFF

Reserved

0x0010 0000 - 0x002F FFFF

 

Aliased to Main Flash or Boot loader

0x0002 0000 - 0x000F FFFF

0x0000 0000 - 0x0001 FFFF

 

GD32F307Zx LQFP144 pin definitions

Table 2-3. GD32F307Zx LQFP144 pin definitions

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4

Alternate:TRACED1, EXMC_A20

 

PE5

 

4

 

I/O

 

5VT

Default: PE5 Alternate:TRACED2, EXMC_A21

Remap: TIMER8_CH0(3)

 

PE6

 

5

 

I/O

 

5VT

Default: PE6 Alternate:TRACED3, EXMC_A22

Remap: TIMER8_CH1(3)

VBAT

6

P

 

Default: VBAT

PC13- TAMPER- RTC

 

7

 

I/O

 

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32IN

 

8

 

I/O

 

Default: PC14 Alternate: OSC32IN

PC15-

OSC32OUT

 

9

 

I/O

 

Default: PC15 Alternate: OSC32OUT

 

PF0

 

10

 

I/O

 

5VT

Default: PF0 Alternate: EXMC_A0

Remap: CTC_SYNC

 

PF1

 

11

 

I/O

 

5VT

Default: PF1 Alternate: EXMC_A1

 

PF2

 

12

 

I/O

 

5VT

Default: PF2

Alternate: EXMC_A2

 

PF3

 

13

 

I/O

 

5VT

Default: PF3 Alternate: EXMC_A3

 

PF4

 

14

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4

 

PF5

 

15

 

I/O

 

5VT

Default: PF5 Alternate: EXMC_A5

VSS_5

16

P

 

Default: VSS_5

VDD_5

17

P

 

Default: VDD_5

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Default: PF6

PF6

18

I/O

 

Alternate: EXMC_NIORD

 

 

 

 

Remap: TIMER9_CH0

 

 

 

 

Default: PF7

PF7

19

I/O

 

Alternate: EXMC_NREG

 

 

 

 

Remap: TIMER10_CH0(3)

 

 

 

 

Default: PF8

PF8

20

I/O

 

Alternate: EXMC_NIOWR

 

 

 

 

Remap: TIMER12_CH0(3)

 

 

 

 

Default: PF9

PF9

21

I/O

 

Alternate: EXMC_CD

 

 

 

 

Remap: TIMER13_CH0(3)

 

PF10

 

22

 

I/O

 

Default: PF10

Alternate: EXMC_INTR

 

OSCIN

 

23

 

I

 

Default: OSCIN

Remap: PD0

 

OSCOUT

 

24

 

O

 

Default: OSCOUT

Remap: PD1

NRST

25

I/O

 

Default: NRST

 

PC0

 

26

 

I/O

 

Default: PC0

Alternate: ADC01_IN10

 

PC1

 

27

 

I/O

 

Default: PC1

Alternate: ADC01_IN11, ENET_MDC

 

PC2

 

28

 

I/O

 

Default: PC2

Alternate: ADC01_IN12, ENET_MII_TXD2

 

PC3

 

29

 

I/O

 

Default: PC3

Alternate: ADC01_IN13, ENET_MII_TX_CLK

VSSA

30

P

 

Default: VSSA

VREF-

31

P

 

Default: VREF-

VREF+

32

P

 

Default: VREF+

VDDA

33

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

34

I/O

 

Alternate: WKUP, USART1_CTS, ADC01_IN0,

TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,

 

 

 

 

TIMER7_ETI, ENET_MII_CRS

 

 

 

 

Default: PA1

PA1

35

I/O

 

Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1,

TIMER4_CH1, ENET_MII_RX_CLK,

 

 

 

 

ENET_RMII_REF_CLK

 

 

 

 

Default: PA2

PA2

36

I/O

 

Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,

 

 

 

 

TIMER4_CH2, TIMER8_CH0(3), ENET_MDIO,

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

SPI0_IO2

 

 

 

 

Default: PA3

PA3

37

I/O

 

Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3,

TIMER4_CH3, TIMER8_CH1(3), ENET_MII_COL,

 

 

 

 

SPI0_IO3

VSS_4

38

P

 

Default: VSS_4

VDD_4

39

P

 

Default: VDD_4

 

 

 

 

Default: PA4

PA4

40

I/O

 

Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,

DAC_OUT0

 

 

 

 

Remap:SPI2_NSS, I2S2_WS

 

PA5

 

41

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

 

 

 

 

Default: PA6

PA6

42

I/O

 

Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,

TIMER7_BRKIN, TIMER12_CH0(3)

 

 

 

 

Remap: TIMER0_BRKIN

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,

PA7

43

I/O

 

TIMER7_CH0_ON, TIMER13_CH0(3),

 

 

 

 

ENET_MII_RX_DV, ENET_RMII_CRS_DV

 

 

 

 

Remap: TIMER0_CH0_ON

 

 

 

 

Default: PC4

PC4

44

I/O

 

Alternate: ADC01_IN14, ENET_MII_RXD0,

 

 

 

 

ENET_RMII_RXD0

 

 

 

 

Default: PC5

PC5

45

I/O

 

Alternate: ADC01_IN15, ENET_MII_RXD1,

 

 

 

 

ENET_RMII_RXD1

 

 

 

 

Default: PB0

PB0

46

I/O

 

Alternate: ADC01_IN8, TIMER2_CH2,

TIMER7_CH1_ON, ENET_MII_RXD2

 

 

 

 

Remap: TIMER0_CH1_ON

 

 

 

 

Default: PB1

PB1

47

I/O

 

Alternate: ADC01_IN9, TIMER2_CH3,

TIMER7_CH2_ON, ENET_MII_RXD3

 

 

 

 

Remap: TIMER0_CH2_ON

PB2

48

I/O

5VT

Default: PB2, BOOT1

 

PF11

 

49

 

I/O

 

5VT

Default: PF11

Alternate: EXMC_NIOS16

 

PF12

 

50

 

I/O

 

5VT

Default: PF12

Alternate: EXMC_A6

VSS_6

51

P

 

Default: VSS_6

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VDD_6

52

P

 

Default: VDD_6

 

PF13

 

53

 

I/O

 

5VT

Default: PF13

Alternate: EXMC_A7

 

PF14

 

54

 

I/O

 

5VT

Default: PF14 Alternate: EXMC_A8

 

PF15

 

55

 

I/O

 

5VT

Default: PF15

Alternate: EXMC_A9

 

PG0

 

56

 

I/O

 

5VT

Default: PG0 Alternate: EXMC_A10

 

PG1

 

57

 

I/O

 

5VT

Default: PG1

Alternate: EXMC_A11

 

PE7

 

58

 

I/O

 

5VT

Default: PE7 Alternate: EXMC_D4

Remap: TIMER0_ETI

 

PE8

 

59

 

I/O

 

5VT

Default: PE8 Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

 

PE9

 

60

 

I/O

 

5VT

Default: PE9

Alternate: EXMC_D6 Remap: TIMER0_CH0

VSS_7

61

P

 

Default: VSS_7

VDD_7

62

P

 

Default: VDD_7

 

PE10

 

63

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

PE11

 

64

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8

Remap: TIMER0_CH1

 

PE12

 

65

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

 

PE13

 

66

 

I/O

 

5VT

Default: PE13

Alternate: EXMC_D10 Remap: TIMER0_CH2

 

PE14

 

67

 

I/O

 

5VT

Default: PE14

Alternate: EXMC_D11 Remap: TIMER0_CH3

 

PE15

 

68

 

I/O

 

5VT

Default: PE15 Alternate: EXMC_D12

Remap: TIMER0_BRKIN

 

PB10

 

69

 

I/O

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX, ENET_MII_RX_ER

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: TIMER1_CH2

 

 

PB11

 

 

70

 

 

I/O

 

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX, ENET_MII_TX_EN, ENET_RMII_TX_EN

Remap: TIMER1_CH3

VSS_1

71

P

 

Default: VSS_1

VDD_1

72

P

 

Default: VDD_1

 

 

PB12

 

 

73

 

 

I/O

 

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS, CAN1_RX,

ENET_MII_TXD0, ENET_RMII_TXD0

 

 

PB13

 

 

74

 

 

I/O

 

 

5VT

Default: PB13

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX, ENET_MII_TXD1, ENET_RMII_TXD1

 

PB14

 

75

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0(3)

 

PB15

 

76

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1(3)

 

 

PD8

 

 

77

 

 

I/O

 

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX, ENET_MII_RX_DV,

ENET_RMII_CRS_DV

 

 

PD9

 

 

78

 

 

I/O

 

 

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX, ENET_MII_RXD0,

ENET_RMII_RXD0

 

 

PD10

 

 

79

 

 

I/O

 

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, ENET_MII_RXD1,

ENET_RMII_RXD1

 

PD11

 

80

 

I/O

 

5VT

Default: PD11 Alternate: EXMC_A16

Remap: USART2_CTS, ENET_MII_RXD2

 

 

PD12

 

 

81

 

 

I/O

 

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS,

ENET_MII_RXD3

 

PD13

 

82

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18

Remap: TIMER3_CH1

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

VSS_8

83

P

 

Default: VSS_8

VDD_8

84

P

 

Default: VDD_8

 

PD14

 

85

 

I/O

 

5VT

Default: PD14

Alternate: EXMC_D0 Remap: TIMER3_CH2

 

PD15

 

86

 

I/O

 

5VT

Default: PD15 Alternate: EXMC_D1

Remap: TIMER3_CH3, CTC_SYNC

 

PG2

 

87

 

I/O

 

5VT

Default: PG2 Alternate: EXMC_A12

 

PG3

 

88

 

I/O

 

5VT

Default: PG3

Alternate: EXMC_A13

 

PG4

 

89

 

I/O

 

5VT

Default: PG4 Alternate: EXMC_A14

 

PG5

 

90

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15

 

PG6

 

91

 

I/O

 

5VT

Default: PG6 Alternate: EXMC_INT1

 

PG7

 

92

 

I/O

 

5VT

Default: PG7

Alternate: EXMC_INT2

PG8

93

I/O

5VT

Default: PG8

VSS_9

94

P

 

Default: VSS_9

VDD_9

95

P

 

Default: VDD_9

 

PC6

 

96

 

I/O

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0

 

PC7

 

97

 

I/O

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1

 

PC8

 

98

 

I/O

 

5VT

Default: PC8

Alternate: TIMER7_CH2 Remap: TIMER2_CH2

 

PC9

 

99

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3 Remap: TIMER2_CH3

 

PA8

 

100

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF, CTC_SYNC

 

PA9

 

101

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

PA10

102

I/O

5VT

Default: PA10

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

 

PA11

 

103

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

 

PA12

 

104

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

 

PA13

 

105

 

I/O

 

5VT

Default: JTMS, SWDIO

Remap: PA13

NC

106

-

-

-

VSS_2

107

P

 

Default: VSS_2

VDD_2

108

P

 

Default: VDD_2

 

PA14

 

109

 

I/O

 

5VT

Default: JTCK, SWCLK

Remap: PA14

 

 

PA15

 

 

110

 

 

I/O

 

 

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

111

 

I/O

 

5VT

Default: PC10 Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

 

PC11

 

112

 

I/O

 

5VT

Default: PC11 Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

 

PC12

 

113

 

I/O

 

5VT

Default: PC12 Alternate: UART4_TX

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

114

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2

Remap: CAN0_RX, OSCIN

 

PD1

 

115

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX, OSCOUT

 

PD2

 

116

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

 

PD3

 

117

 

I/O

 

5VT

Default: PD3 Alternate: EXMC_CLK

Remap: USART1_CTS

 

PD4

 

118

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

119

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

 

 

Remap: USART1_TX

VSS_10

120

P

 

Default: VSS_10

VDD_10

121

P

 

Default: VDD_10

 

PD6

 

122

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT Remap: USART1_RX

 

PD7

 

123

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

124

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2

 

PG10

 

125

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2

 

PG11

 

126

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1

 

PG12

 

127

 

I/O

 

5VT

Default: PG12

Alternate: EXMC_NE3

 

PG13

 

128

 

I/O

 

5VT

Default: PG13

Alternate: EXMC_A24

 

PG14

 

129

 

I/O

 

5VT

Default: PG14

Alternate: EXMC_A25

VSS_11

130

P

 

Default: VSS_11

VDD_11

131

P

 

Default: VDD_11

PG15

132

I/O

5VT

Default: PG15

 

 

PB3

 

 

133

 

 

I/O

 

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1,

SPI0_SCK

 

PB4

 

134

 

I/O

 

5VT

Default: NJTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

 

PB5

 

 

135

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD, ENET_MII_PPS_OUT, ENET_RMII_PPS_OUT

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

 

PB6

 

136

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX, SPI0_IO2

 

PB7

 

137

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX, SPI0_IO3

BOOT0

138

I

 

Default: BOOT0

 

 

 

Pin Name

 

 

Pins

 

 

Pin Type(1)

 

 

I/O Level(2)

 

 

Functions description

 

 

PB8

 

 

139

 

 

I/O

 

 

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0(3), ENET_MII_TXD3

Remap: I2C0_SCL, CAN0_RX

 

PB9

 

140

 

I/O

 

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0(3) Remap: I2C0_SDA, CAN0_TX

 

PE0

 

141

 

I/O

 

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0

 

PE1

 

142

 

I/O

 

5VT

Default: PE1

Alternate: EXMC_NBL1

VSS_3

143

P

 

Default: VSS_3

VDD_3

144

P

 

Default: VDD_3

Notes:
(1)Type: I = input, O = output, P = power. 
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available in GD32F307ZG devices.

3.1.ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
Floating Point Unit (FPU)


3.2.On-chip memory

Up to 1024 Kbytes of Flash memory, including code Flash and data Flash
96 KB of SRAM

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner flash at most, which includes code Flash that available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. An extra data Flash is also included for storing data mainly. Table 2-2. GD32F307xx memory map shows the memory of the GD32F307xx

series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.


Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 120 MHz The maximum frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz See Figure 2-5 GD32F307xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6) and USBFS (PA9, PA11 and PA12) is also available for boot functions. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default

condition, boot from bank0 of Flash memory is selected. It also supports to boot from bank1 of Flash memory by setting a bit in option bytes.

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, the USB wakeup and ENET wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.6 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to two 12-bit 2.6 MSPS multi-channel ADCs are integrated in the device. It has a total of 18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), and 1 channel for internal reference voltage (VREFINT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.

The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

Two 12-bit DACs with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller

The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.

3.8.DMA

7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 112 general purpose I/O pins (GPIO) in GD32F307xx, named PA0 ~ PA15 and  PB0  ~ PB15,  PC0  ~  PC15,  PD0  ~ PD15,  PE0  ~  PE15,  PF0-PF15,  PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-

up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge-aligned or center-aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 ~ TIMER4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~ TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F307xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in

debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wakeup event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides several data transfer rates of up to 100 KHz in standard mode, up to 400 KHz in fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode

Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI0.

Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs and two UARTs with operating frequency up to 7.5M Bits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication except UART4.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F307xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.

Universal serial bus full-speed interface (USBFS)

One USB device/host/full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator (IRC48M) support crystal-less operation
Internal main PLL for USBCLK compliantly
Internal USBFS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator (IRC48M) in automatic trimming mode that allows crystal-less operation.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Ethernet (ENET)

IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 16 with 25 MHz output and RMII up to 7 with 50 MHz output. The function of 32-bit CRC checking is also available.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and PC card
Provide ECC calculating hardware module for NAND Flash memory block
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and PC card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP144 (GD32F307Zx), LQFP100 (GD32F307Vx) and LQFP64 (GD32F307Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

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发布时间: : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用,如今,家用电器的智能化已成为一种常态,越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入,今天就来说说这个话题。 什么是智能浴室镜?智慧型浴室镜,顾名思义,就是卫浴镜子智能化升级,入门级产品基本具备了彩灯和镜面触摸功能,更高档次的产品安装有微波雷达传感器智能感应,当感应到有人接近到一定距离即可开启亮灯或者亮屏操作,也可三色无极调,智能除雾,语音交互,日程安排备忘,甚至在镜子上看电视,听音乐,气象预报,问题查询,智能控制,健康管理等。 智能化雷达感应浴室镜与普通镜的区别,为什么要选TA?,就功能而言,普通浴镜价格用它没有什么压力!而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言,普通浴镜功能单一,而微波雷达传感器智能浴室镜功能创新:镜子灯光色温和亮度可以自由调节,镜面还可以湿手触控,智能除雾,既环保又健康! 尽管智能浴镜比较新颖,但功能丰富,体验感更好,特别是入门级的智能浴镜,具有基础智能化功能,真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么? ①确定智能浴室镜的安装位置,因为是安装时在墙壁上打孔,一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时,根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后,在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度,一般智能浴镜的标准安装高度约85cm(从地砖到镜子底),具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍,可用酒精或30%清洁稀释液擦洗,平时可用干毛巾养护,注意多通风。
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发布时间: : 2022-02--07
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29
2022-09

蓝牙Beacon 2.4G wifi无线模组特点门铃场景中的应用

发布时间: : 2022-09--29
蓝牙Beacon 2.4G wifi无线模组特点门铃场景中的应用,低功耗蓝牙Beacon技术让很多商家产生了兴趣,通过Beacon技术向兼容的移动设备发送信号,可以推广商品以及活动信息等吸引消费者。Beacon 2.4G wifi无线模组通过蓝牙的广播和扫描协议进行通讯,下面介绍Beacon 2.4G无线模块的特点,以及应用在哪些项目中。 Beacon 2.4G wifi无线模组的特点 1.可与手机相连的2.4G模块 2.可与BLE设备相互通讯 3.支持开发Beacon、iBeacon协议 4.通过蓝牙的广播和扫描协议进行通讯 蓝牙Beacon 2.4G wifi无线模组一般在哪些项目中使用 一、商场、展柜消息推送 当消费者在商场中靠近某个安装有Beacon设备的展柜一定范围时,如果消费者的手机与Beacon设备相兼容,那么就可以推送消息给消费者,比如通知消费者有哪些新品,哪些产品正在打折等等,以这样的方式刺激消费访问商家。 二、室内定位 将beacon设备放置在某些场所,可以了解到用户位置的变化。 将距离简单分为三级。苹果在iOS中并不仔细推断距离,将距离分为贴近贴近(Immediate)、1m以内(Near)、1m以上(Far)三种距离状态。 距离在1m以内时,RSSI值基本上成比例减少,而距离在1m以上时,由于反射波的影响等,RSSI不减少而是上下波动。也就是说,相距1m以上时无法推断距离,因此就简单判定为Far。 三、数据传送(温湿度传送) 可以将采集的温度通过Beacon广播发给手机。 以上就是Beacon 2.4G wifi无线模组的特点,这款产品常应用在无线鼠标、无线健康运动产品、商品信息推送、无线遥感、报警安保系统、无线测距系统等行业中。 2.4G wifi无线模组在门铃场景中的应用,门铃是现代生活常见的一个生活家具,它可以用于城市中的高楼大厦、高层住宅、甚至我们的民间楼房都可以使用到门铃。门铃从只有客人叫门的作用,发展到现在门户信息之间的传递、大门控制、出现紧急情况向门卫报警等等功能,都预示着门铃不断向着智能发现发展。 传统的门铃安装方式都是有线安装,发射器和接收器都是依靠电线连接的,发射器发出的信号是通过电线传输至接收器,所以有线门铃大优势就是它的信号比较稳定,也不会发生误响等情况,但是由于布线比较麻烦,很可能需要凿墙等,在如今遍地都是高楼大厦的城市中,显得很是麻烦,因而近几年逐渐淡出市场。 有线门铃的淡出,也意味着无线门铃的兴起,现在一栋栋的高楼大厦不断的建设当中,无线门铃的应用市场也是相当的巨大。那么大家知道无线门铃的原理是什么吗? 无线门铃关键的一点,就是如何取代有线方式的信号传输问题?现在市面上的无线门铃是在发射器和接收器中各安装一个2.4Gwifi无线模组来代替线缆的信号传输,无线模块可以很有效的解决凿墙布线的问题,还可以节省不少的成本,成为当下主流的无线门铃选择方案。 但是市面有各式各样,不同类型的无线模块,那么无线门铃一般都是选择那种来使用呢?大家都知道门铃的价格一直都是非常的便宜,所以2.4Gwifi无线模组就成为了无线门铃的首选,有人会问了,为什么不是选择同样便宜的蓝牙模块呢?那是因为蓝牙模块的传输距离比较短,且蓝牙模块之间只能点对点使用,不符合实际的应用场景。 2.4G wifi无线模组是可以进行二次开发的,通过单片机,写入一段程序,控制无线模块进行工作。无线模块就设有一个数据端口方便用户直接连接单片机,目的就是为了用户研发和生产的时候更加方便快捷。
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28
2022-09

远距离WiFi模块抗干扰能力的提高

发布时间: : 2022-09--28
远距离WiFi模块抗干扰能力的提高,远距离WiFi模块的抗干扰能力是无法进行具体数值化,所以它一般不会做为常规参数放在无线模块的规格书里,那么无线模块的抗干扰能力到底重不重要呢?答案是:非常重要。在同一发射功率和接收灵敏度的条件下,那么抗干扰能力更强的无线模块可以传输的距离会更远。 为什么提高抗干扰能力会提高通讯距离呢?远距离WiFi模块在收发通讯时,干扰源是无处不在的(磁场、金属、墙壁等),信号在空中发射时就会受到干扰源的不断干扰,导致信号强度会不断衰弱,到信号衰减到一定程度时,接收机就会接收不到发射过来的信号,从而导致通讯距离的缩短。 干扰源可以完全规避吗?哪怕是有线的通讯方式也会存在干扰的情况,所以我们没有办法去完全规避掉干扰源,所以好的办法就是提高无线模块的抗干扰能力,那么提高远距离WiFi模块抗干扰能力有哪些呢? 1. 远离干扰源 尽量避免在干扰源多的地方使用无线模块(避开干扰源是有效且直接的办法)。 2. 带宽 在无线通讯领域中,带宽越窄,代表着抗干扰能力就越好,所以适当的修改无线模块的带宽,可以很好提升无线模块在通讯时的抗干扰能力。 3. 降低传输速率 传输速率越快,会导致信号强度衰减的越快,适当的降低传输速率可以增强信号强度,从而提升无线模块的抗干扰能力。 4. 定向天线 我们发射远距离WiFi模块可以采用高增益的定向天线,定向天线它可以指定某一个或者多个方向发射及接收电磁波特别强,而在其他的方向上发射及接收电磁波则为零或极小的一种天线。定向天线的用处就是可以增加信号的强度,从而提升无线模块的抗干扰能力。 5. 屏蔽罩 屏蔽罩是无线模块提高的抗干扰能力好一个办法,屏蔽罩的可以屏蔽掉一定外界干扰源对芯片的影响,同时也能防止无线模块工作时对外界产生干扰和辐射。 6. 滤波器 滤波器是根据频率来区分的,例如:433MHz就只能使用对应频率的滤波器,它主要的功能是过滤掉其他不属于433MHz的频率,防止受到其他频段的干扰,从而达到抗干扰能力的效果。 今天的如何提高远距离WiFi模块的抗干扰能力就到这里结束了,如果您还有更好的提高抗干扰能力的方法也可以分享给我们,欢迎大家随时联系我司。 远距离WiFi模块为什么要加屏蔽罩外壳?作为现代化物联网中重要的一个环节,在市场上的可以说是非常受欢迎的。远距离WiFi模块的种类也可以说是五花八门,各种功能的无线模块在市面上都逐一崭露头角。但是大家有注意到大部分无线模块都会带有一个金属外壳吗?又知道这个金属外壳对无线模块能起到什么作用吗? 远距离WiFi模块上的金属外壳叫屏蔽罩,属于无线模块一个硬件设施之一,它的主要作用分为两个: 1.防止无线模块工作时对外界产生干扰和辐射;功率越大的无线模块产生的干扰和辐射也会相应的越大,所以加一个金属外壳可以在一定程度上减小这些干扰和辐射。 2.屏蔽外界对远距离WiFi模块产生干扰;在无线模块的工作环境当中,有很多复杂干扰源,如外界电场、磁场这种看不见也摸不着干扰源用存在着。但是,给无线模块加上屏蔽罩之后,就可以很好的隔绝了这些外界的干扰源。 那么屏蔽罩的工作原理是什么呢?用屏蔽罩将需要保护的继电器、芯片、单片机、电路板等重要功能元器件包围起来,从而形成一个保护圈,既可以有效防止无线模块产生的辐射干扰对外扩散,也可以防止外界干扰源对无线模块的正常工作产生干扰。 屏蔽罩的注意事项: 1.屏蔽罩并不是必需品,我们可以根据实际的情况来判断无线模块是否需要带屏蔽罩。例如考虑到成本、外观、实际设备使用情况等判断是否需要屏蔽罩。 2.使用屏蔽罩时,要考虑的因素有很多,例如屏蔽罩的尺寸大小、屏蔽罩离电子元器件的距离、屏蔽罩的材料等等,这些因素都是非常重要的;因为屏蔽罩设计的不够理想的话,很有可能会影响无线模块的性能。思为无线每一款无线模块上的屏蔽罩都是我司硬件工程师精心设计而成的,可以屏蔽大部分外界干扰,保证模块的正常工作。 总得来说,屏蔽罩对远距离WiFi模块是非常重要的,一是它可以提高无线模块的抗干扰能力,二是抗干扰能力越强也相对应的会提升模块的传输距离,所以无线模块加一个屏蔽罩外壳还是非常有必要的。但是,屏蔽罩并不是无线模块的必需品,这点在上文的注意事项中说得很清楚。  
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27
2022-09

智能家电wifi模组常见问题天线长度与频率波长的关系

发布时间: : 2022-09--27
智能家电wifi模组常见问题天线长度与频率波长的关系,智能家电wifi模组块在使用过程中,往往会遇见各种问题,今天整理了一份近几年来,客户常遇见的问题,希望能帮助到大家。 1. 智能家电wifi模组死机 1)查供电电源(电源负载电流是否比模块规格书上的发射电流大,电源类型) 2)是否影响到别的设备。(工作环境中,是否有其他的无线设备) 2. 智能家电wifi模组正常使用一段时间后,通讯距离越来越短怎么办? 这种情况,一般是硬件电路损坏,需要寄回维修。 3. 智能家电wifi模组发射不出信号或者通讯不上? 1)检查模块硬件接线是否有问题 2)看SPI是否能读寄存器值,如果是则说明接线正确,否则反之。 3)检查供电,是否达到工作电压(可通过降低功率确定) 4. 是否支持跳频功能? 不支持芯片自动跳频,需单片机设置频率 5. 同样的程序,在别的厂商的无线模块上可以正常工作,为什么我司的维修模块不能正常工作? 不同厂家的无线模块的天线、晶振不同,所以程序不一定匹配。 6. 我司的智能家电wifi模组是否能和别的厂商通讯? 实际的频率不一样,不能和别的厂商的无线模块通讯。(实际频率要用频谱仪测试) 7. 无线模块为什么发烫? 天线开关没有控制好。 8. 智能家电wifi模组怎么进入休眠状态? 用SPI接口发送指令,具体可参考我司对应的模块DOMO程序。 9. 无线模块怎么修改速率/频率?或某个无线模块速率/频率对应的参数值是多少? 每个无线模块都有寄存器手册或者配置软件,计算出需要修改的寄存器值,可通过SPI接口发送指令给无线模块 10. 智能家电wifi模组怎么设置功率? 每个无线模块的规格书都可以查看相对应的功率对照表。 11. 模块休眠时,为何接收不到数据? 无线模块在休眠状态时,是处于关闭无线的状态,这种情况下是无法接收数据 12. 无线模块如何从休眠中唤醒? 通过SPI接口发送任何指令。 13. 智能家电wifi模组如何实现无线远程唤醒? 除si4463模块有自带的LDC功能外,其他的前端无线模块都需单片机定时控制模块在休眠和接收中切换。 14. 无线模块一次可以发送多少字节? FSK系列模块的一次64字节,LORA系列模块一次255个字节,2.4G系列一次32个字节 15. 智能家电wifi模组如何实现大数据发送? 我们需要通过单片机设置好进行分包发送。 智能家电wifi模组常见的问题大概整理15条,希望能够帮助到大家。相关常见问题,也会近日整理出给到大家。如果您还有其他的问题欢迎联系我们。 天线长度与频率、波长的关系 天线在通信领域使用的范围很广,有的客户不知道天线长度和频率、波长有什么关系,天线长度的计算公式是什么,有时候看到网上卖的同频率的天线有长有短,心里疑惑不已,下面为大家分析天线长度与频率、波长的关系。 智能家电wifi模组天线长度与频率、波长的关系 天线长度与频率成反比,与波长成正比,频率越高,波长越短,天线也就可以做得越短。 天线长度计算公式 当天线的长度为波长的1/4时,天线的发射和接收转换效率高。 因此,天线的长度将根据所发射和接收信号的频率即波长来决定。用下面的公式可以计算出波长,然后将算出的波长除以4就是对应的佳天线长度。 频率与波长的换算公式为: 波长=30万公里/频率 =300000000米/频率 (得到的单位为米)) 例如:无线数传电台使用的信号频率为435MHz,波长为: 波长= 300000公里/435MHz = 300000000/435000000 = 300/435 = 0.69米 对应的天线长度应为 0.69/4 ,等于0.1725米 以上就是天线长度与频率|波长的关系,天线的长度中心工作频率的波长有直接关系,在购买的时候我们也许会发现天线似乎没有那么长,那是因为厂家用加感的方式缩短长度,如果把里面一圈圈的线材拉直,长度也是接近波长的四分之一的。
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