这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F330G8U6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F330G8U6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F330xx ARM® Cortex®-M4 32-bit MCU Datasheet General description The GD32F330xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support. The GD32F330xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 84 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, up to five general 16-bit timers, a general 32-bit timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F330xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.   Part Number GD32F330xx   F4 F6 F8 G4 G6 G8 K4 K6 K8 C4 C6 C8 CB R8 RB Flash Code area (KB)   16   32   64   16   32   64   16   32   64   16   32   64   64   64   64   Data area (KB)   0   0   0   0   0   0   0   0   0   0   0   0   64   0   64   Total (KB) 16 32 64 16 32 64 16 32 64 16 32 64 128 64 128 SRAM (KB) 4 4 8 4 4 8 4 4 8 4 4 8 16 16 16 Timers Genaral timer (32-bit) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1)   Genaral timer (16-bit) 4 (2,13,15,16) 4 (2,13,15,16) 4 (2,13,15,16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16)   Advanced timer (16-bit) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0)   SysTick 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F330G8U6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F330xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

General description

The GD32F330xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support.
The GD32F330xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 84 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, up to five general 16-bit timers, a general 32-bit timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F330xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.

 

Part Number

GD32F330xx

 

F4

F6

F8

G4

G6

G8

K4

K6

K8

C4

C6

C8

CB

R8

RB

Flash

Code area

(KB)

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

64

 

64

 

64

 

Data area

(KB)

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

64

 

0

 

64

 

Total (KB)

16

32

64

16

32

64

16

32

64

16

32

64

128

64

128

SRAM (KB)

4

4

8

4

4

8

4

4

8

4

4

8

16

16

16

Timers

Genaral timer

(32-bit)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

 

Genaral timer

(16-bit)

4

(2,13,15,16)

4

(2,13,15,16)

4

(2,13,15,16)

4

(2,13,15,16)

4

(2,13,15,16)

5

(2,13-16)

4

(2,13,15,16)

4

(2,13,15,16)

5

(2,13-16)

4

(2,13,15,16)

4

(2,13,15,16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

 

Advanced

timer (16-bit)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

 

SysTick

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Connectivity

 

USART

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

 

 

I2C

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

 

 

SPI

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

GPIO

15

15

15

23

23

23

27

27

27

39

39

39

39

55

55

EXTI

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

ADC

Units

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Channels

(External)

9

9

9

10

10

10

10

10

10

10

10

10

10

16

16

 

Channels

(Internal)

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

Package

TSSOP20

QFN28

QFN32

LQFP48

LQFP64

 

Memory map

Table 2-2. GD32F330xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0xE000 0000 - 0xE00F FFFF

Cortex-M4 internal peripherals

External Device

 

0xA000 0000 - 0xDFFF FFFF

Reserved

External RAM

 

0x6000 0000 - 0x9FFF FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripherals

 

AHB1

0x5004 0000 - 0x5FFF FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

Reserved

 

 

 

 

 

AHB2

0x4800 1800 - 0x4FFF FFFF

Reserved

 

 

0x4800 1400 - 0x4800 17FF

GPIOF

 

 

0x4800 1000 - 0x4800 13FF

Reserved

 

 

0x4800 0C00 - 0x4800 0FFF

GPIOD

 

 

0x4800 0800 - 0x4800 0BFF

GPIOC

 

 

0x4800 0400 - 0x4800 07FF

GPIOB

 

 

0x4800 0000 - 0x4800 03FF

GPIOA

 

 

 

 

 

 

 

AHB1

0x4002 4400 - 0x47FF FFFF

Reserved

 

 

0x4002 4000 - 0x4002 43FF

Reserved

 

 

0x4002 3400 - 0x4002 3FFF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1400 - 0x4002 1FFF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0400 - 0x4002 0FFF

Reserved

 

 

0x4002 0000 - 0x4002 03FF

DMA

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 8000 - 0x4001 FFFF

Reserved

 

 

0x4001 5C00 - 0x4001 7FFF

Reserved

 

 

0x4001 4C00 - 0x4001 5BFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER16

 

 

0x4001 4400 - 0x4001 47FF

TIMER15

 

 

0x4001 4000 - 0x4001 43FF

TIMER14

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

Reserved

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

Reserved

 

 

0x4001 2400 - 0x4001 27FF

ADC

 

 

0x4001 0800 - 0x4001 23FF

Reserved

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 0000 - 0x4001 03FF

SYSCFG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

CTC

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

Reserved

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6400 - 0x4000 6FFF

Reserved

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 4800 - 0x4000 53FF

Reserved

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

Reserved

 

 

0x4000 3800 - 0x4000 3BFF

SPI1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1400 - 0x4000 1FFF

Reserved

 

 

0x4000 1000 - 0x4000 13FF

Reserved

 

 

0x4000 0800 - 0x4000 0FFF

Reserved

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

SRAM

 

0x2000 4000 - 0x3FFF FFFF

Reserved

 

 

0x2000 0000 - 0x2000 3FFF

SRAM

 

 

 

 

Code

 

0x1FFF FC00 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF FBFF

Option bytes

 

 

0x1FFF EC00 - 0x1FFF F7FF

System memory

 

 

0x0802 0000 - 0x1FFF EBFF

Reserved

 

 

0x0800 0000 - 0x0801 FFFF

Main Flash memory

 

 

0x0010 0000 - 0x07FF FFFF

Reserved

 

 

0x0000 0000 - 0x000F FFFF

Aliased to Flash or system memory

 

GD32F330Rx LQFP64 pin definitions

Table 2-3. GD32F330Rx LQFP64 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13- TAMPER-

RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

PF0-OSCIN

 

5

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1- OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

 

PC0

 

8

 

I/O

 

Default: PC0

Alternate: EVENTOUT Additional: ADC_IN10

 

PC1

 

9

 

I/O

 

Default: PC1

Alternate: EVENTOUT Additional: ADC_IN11

 

PC2

 

10

 

I/O

 

Default: PC2 Alternate: EVENTOUT

Additional: ADC_IN12

 

PC3

 

11

 

I/O

 

Default: PC3

Alternate: EVENTOUT Additional: ADC_IN13

VSSA

12

P

 

Default: VSSA

VDDA

13

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

14

 

 

I/O

 

Default: PA0

Alternate: USART1_CTS, TIMER1_CH0, TIMER1_ETI, I2C1_SCL

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

PA1

 

 

15

 

 

I/O

 

Default: PA1

Alternate: USART1_RTS, TIMER1_CH1, I2C1_SDA, EVENTOUT

Additional: ADC_IN1

 

PA2

 

16

 

I/O

 

Default: PA2

Alternate: USART1_TX, TIMER1_CH2, TIMER14_CH0

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Additional: ADC_IN2

 

 

 

 

Default: PA3

PA3

17

I/O

 

Alternate: USART1_RX, TIMER1_CH3, TIMER14_CH1

 

 

 

 

Additional: ADC_IN3

 

PF4

 

18

 

I/O

 

5VT

Default: PF4

Alternate: EVENTOUT

 

PF5

 

19

 

I/O

 

5VT

Default: PF5

Alternate: EVENTOUT

 

 

 

 

Default: PA4

PA4

20

I/O

 

Alternate: SPI0_NSS, USART1_CK, TIMER13_CH0,

SPI1_NSS

 

 

 

 

Additional: ADC_IN4

 

 

 

 

Default: PA5

PA5

21

I/O

 

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

 

 

 

 

Additional: ADC_IN5

 

 

 

 

Default: PA6

PA6

22

I/O

 

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN,

TIMER15_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

PA7

23

I/O

 

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,

TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PC4

PC4

24

I/O

 

Alternate: EVENTOUT

 

 

 

 

Additional: ADC_IN14

 

PC5

 

25

 

I/O

 

Default: PC5

Additional: ADC_IN15, WKUP4

 

 

 

 

Default: PB0

PB0

26

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

27

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK

 

 

 

 

Additional: ADC_IN9

PB2

28

I/O

5VT

Default: PB2

 

PB10

 

29

 

I/O

 

5VT

Default: PB10

Alternate: I2C1_SCL, TIMER1_CH2, SPI1_IO2

 

 

 

 

Default: PB11

PB11

30

I/O

5VT

Alternate:I2C1_SDA, TIMER1_CH3, EVENTOUT,

 

 

 

 

SPI1_IO3

VSS

31

P

 

Default: VSS

VDD

32

P

 

Default: VDD

PB12

33

I/O

5VT

Default: PB12

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: SPI1_NSS, TIMER0_BKIN, I2C1_SMBA,

 

 

 

 

EVENTOUT

 

PB13

 

34

 

I/O

 

5VT

Default: PB13

Alternate: SPI1_SCK, TIMER0_CH0_ON

 

 

 

 

Default: PB14

PB14

35

I/O

5VT

Alternate: SPI1_MISO, TIMER0_CH1_ON,

 

 

 

 

TIMER14_CH0

 

 

 

 

Default: PB15

 

PB15

 

36

 

I/O

 

5VT

Alternate: SPI1_MOSI, TIMER0_CH2_ON,

TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

PC6

 

37

 

I/O

 

5VT

Default: PC6

Alternate: TIMER2_CH0

 

PC7

 

38

 

I/O

 

5VT

Default: PC7

Alternate: TIMER2_CH1

 

PC8

 

39

 

I/O

 

5VT

Default: PC8

Alternate: TIMER2_CH2

 

PC9

 

40

 

I/O

 

5VT

Default: PC9

Alternate: TIMER2_CH3

 

 

 

 

Default: PA8

PA8

41

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX, EVENTOUT,CTC_SYNC

 

 

 

 

Default: PA9

PA9

42

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,

 

 

 

 

I2C0_SCL

 

 

 

 

Default: PA10

PA10

43

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

I2C0_SDA

 

 

 

 

Default: PA11

PA11

44

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,

 

 

 

 

SPI1_IO2

 

 

 

 

Default: PA12

PA12

45

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,

 

 

 

 

SPI1_IO3

 

PA13

 

46

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO

 

PF6

 

47

 

I/O

 

5VT

Default: PF6

Alternate: I2C1_SCL

 

PF7

 

48

 

I/O

 

5VT

Default: PF7

Alternate: I2C1_SDA

 

PA14

 

49

 

I/O

 

5VT

Default: PA14

Alternate: USART1_TX, SWCLK, SPI1_MOSI

 

 

 

 

Default: PA15

PA15

50

I/O

5VT

Alternate: SPI0_NSS , USART1_RX, TIMER1_CH0,

 

 

 

 

TIMER1_ETI, SPI1_NSS, EVENTOUT

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PC10

51

I/O

5VT

Default: PC10

PC11

52

I/O

5VT

Default: PC11

PC12

53

I/O

5VT

Default: PC12

 

PD2

 

54

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI

 

PB3

 

55

 

I/O

 

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

 

PB4

 

56

 

I/O

 

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

PB5

 

 

57

 

 

I/O

 

 

5VT

Default: PB5

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1

Additional:WKUP5

 

PB6

 

58

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

 

PB7

 

59

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

60

I

 

Default: BOOT0

 

PB8

 

61

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

 

PB9

 

62

 

I/O

 

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0,

EVENTOUT

VSS

63

P

 

Default: VSS

VDD

64

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330C4 devices only.
(4)Functions are available on GD32F330CB/8/6 devices.
(5)Functions are available on GD32F330CB/8 devices.

GD32F330Cx LQFP48 pin definitions

Table 2-4. GD32F330Cx LQFP48 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13-

TAMPER- RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

 

 

 

Default: PF0

PF0-OSCIN

5

I/O

5VT

Alternate: CTC_SYNC

 

 

 

 

Additional: OSCIN

PF1-

OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

VSSA

8

P

 

Default: VSSA

VDDA

9

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

10

I/O

 

Alternate: USART0_CTS(3), USART1_CTS(4),

TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

 

 

 

 

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

 

 

Default: PA1

PA1

11

I/O

 

Alternate: USART0_RTS(3), USART1_RTS(4),

TIMER1_CH1, I2C1_SDA(5), EVENTOUT

 

 

 

 

Additional: ADC_IN1

 

 

 

 

Default: PA2

PA2

12

I/O

 

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,

TIMER14_CH0

 

 

 

 

Additional: ADC_IN2

 

 

 

 

Default: PA3

PA3

13

I/O

 

Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3,

TIMER14_CH1

 

 

 

 

Additional: ADC_IN3

 

 

 

 

Default: PA4

PA4

14

I/O

 

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),

TIMER13_CH0, SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4

 

 

 

 

Default: PA5

PA5

15

I/O

 

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

 

 

 

 

Additional: ADC_IN5

 

 

 

 

Default: PA6

PA6

16

I/O

 

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN,

TIMER15_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

PA7

17

I/O

 

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,

TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

18

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PB1

PB1

19

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

PB2

20

I/O

5VT

Default: PB2

 

 

 

 

Default: PB10

PB10

21

I/O

5VT

Alternate: I2C0_SCL(3),I2C1_SCL(5), TIMER1_CH2,

 

 

 

 

SPI1_IO2(5)

 

 

 

 

Default: PB11

PB11

22

I/O

5VT

Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3,

 

 

 

 

EVENTOUT, SPI1_IO3(5)

VSS

23

P

 

Default: VSS

VDD

24

P

 

Default: VDD

 

 

 

 

Default: PB12

PB12

25

I/O

5VT

Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN,

 

 

 

 

I2C1_SMBA(5), EVENTOUT

 

PB13

 

26

 

I/O

 

5VT

Default: PB13

Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON

 

 

 

 

Default: PB14

PB14

27

I/O

5VT

Alternate: SPI0_MISO(3), SPI1_MISO(5),

 

 

 

 

TIMER0_CH1_ON, TIMER14_CH0

 

 

 

 

Default: PB15

 

PB15

 

28

 

I/O

 

5VT

Alternate: SPI0_MOSI(3), SPI1_MOSI(5),

TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

 

 

 

Default: PA8

PA8

29

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,CTC_SYNC

 

 

 

 

Default: PA9

PA9

30

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,

 

 

 

 

I2C0_SCL

 

 

 

 

Default: PA10

PA10

31

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

I2C0_SDA

 

 

 

 

Default: PA11

PA11

32

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,

 

 

 

 

SPI1_IO2(5)

 

 

 

 

Default: PA12

PA12

33

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,

 

 

 

 

SPI1_IO3(5)

 

PA13

 

34

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PF6

 

35

 

I/O

 

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PF7

36

I/O

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

 

PA14

 

37

 

I/O

 

5VT

Default: PA14

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

 

PA15

 

38

 

I/O

 

5VT

Default: PA15

Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT

PB3

39

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

PB4

40

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

PB5

 

 

41

 

 

I/O

 

 

5VT

Default: PB5

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1

Additional:WKUP5

 

PB6

 

42

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

PB7

43

I/O

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

44

I

 

Default: BOOT0

PB8

45

I/O

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

 

PB9

 

46

 

I/O

 

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0,

EVENTOUT

VSS

47

P

 

Default: VSS

VDD

48

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330C4 devices only.
(4)Functions are available on GD32F330CB/8/6 devices.
(5)Functions are available on GD32F330CB/8 devices.

GD32F330Kx QFN32 pin definitions

Table 2-5. GD32F330Kx QFP32 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0

Alternate: CTC_SYNC Additional: OSCIN

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PF1-

OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

6

I/O

 

Alternate: USART0_CTS(3), USART1_CTS(4),

TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

 

 

 

 

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

 

 

Default: PA1

PA1

7

I/O

 

Alternate: USART0_RTS(3), USART1_RTS(4),

TIMER1_CH1, I2C1_SDA(5), EVENTOUT

 

 

 

 

Additional: ADC_IN1

 

 

 

 

Default: PA2

PA2

8

I/O

 

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,

TIMER14_CH0

 

 

 

 

Additional: ADC_IN2

 

 

 

 

Default: PA3

PA3

9

I/O

 

Alternate: USART0_RX(3), USART1_RX(4),

TIMER1_CH3, TIMER14_CH1

 

 

 

 

Additional: ADC_IN3

 

 

 

 

Default: PA4

PA4

10

I/O

 

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),

TIMER13_CH0, SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4

 

 

 

 

Default: PA5

PA5

11

I/O

 

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

 

 

 

 

Additional: ADC_IN5

 

 

 

 

Default: PA6

PA6

12

I/O

 

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN,

TIMER15_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

PA7

13

I/O

 

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,

TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

14

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

15

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

PB2

16

I/O

5VT

Default: PB2

VDD

17

P

 

Default: VDD

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PA8

 

18

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT,CTC_SYNC

 

PA9

 

19

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL

 

PA10

 

20

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

I2C0_SDA

 

PA11

 

21

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT, SPI1_IO2(5)

 

PA12

 

22

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5)

 

PA13

 

23

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PA14

 

24

 

I/O

 

5VT

Default: PA14

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

 

PA15

 

25

 

I/O

 

5VT

Default: PA15

Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT

PB3

26

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

PB4

27

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

PB5

 

 

28

 

 

I/O

 

 

5VT

Default: PB5

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1

Additional:WKUP5

PB6

29

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

 

PB7

 

30

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

31

I

 

Default: BOOT0

PB8

32

I/O

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

VDD

1

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330K4 devices only.
(4)Functions are available on GD32F330KB/8/6 devices.

(5)Functions are available on GD32F330KB/8 devices.

GD32F330Gx QFN28 pin definitions

Table 2-6. GD32F330Gx QFN28 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1- OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

6

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

PA1

 

 

7

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1

 

 

PA2

 

 

8

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0

Additional: ADC_IN2

 

 

PA3

 

 

9

 

 

I/O

 

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1

Additional: ADC_IN3

 

 

PA4

 

 

10

 

 

I/O

 

Default: PA4

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Additional: ADC_IN4

 

PA5

 

11

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

Additional: ADC_IN5

 

 

PA6

 

 

12

 

 

I/O

 

Default: PA6

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT

Additional: ADC_IN6

 

 

PA7

 

 

13

 

 

I/O

 

Default: PA7

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

Additional: ADC_IN7

 

PB0

 

14

 

I/O

 

Default: PB0

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

USART1_RX, EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

15

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

VSS

16

P

 

Default: VSS

VDD

17

P

 

Default: VDD

 

 

 

 

Default: PA8

PA8

18

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX, EVENTOUT,CTC_SYNC

 

 

 

 

Default: PA9

PA9

19

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,

 

 

 

 

I2C0_SCL

 

 

 

 

Default: PA10

PA10

20

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

I2C0_SDA

 

PA13

 

21

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

 

 

 

Default: PA14

PA14

22

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

23

I/O

5VT

Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4),

 

 

 

 

TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT

 

PB3

 

24

 

I/O

 

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

 

PB4

 

25

 

I/O

 

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

 

 

Default: PB5

PB5

26

I/O

5VT

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN,

TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

PB6

 

27

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

 

PB7

 

28

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

1

I

 

Default: BOOT0

 

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330G4 devices only.
(4)Functions are available on GD32F330GB/8/6 devices.
(5)Functions are available on GD32F330GB/8 devices.

GD32F330Fx TSSOP20 pin definitions

Table 2-7. GD32F330Fx TSSOP20 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0

Alternate: CTC_SYNC Additional: OSCIN

PF1- OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

6

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

PA1

 

 

7

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1

 

 

PA2

 

 

8

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0

Additional: ADC_IN2

 

 

PA3

 

 

9

 

 

I/O

 

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1

Additional: ADC_IN3

 

 

PA4

 

 

10

 

 

I/O

 

Default: PA4

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Additional: ADC_IN4

 

PA5

 

11

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

Additional: ADC_IN5

 

 

PA6

 

 

12

 

 

I/O

 

Default: PA6

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT

Additional: ADC_IN6

 

 

PA7

 

 

13

 

 

I/O

 

Default: PA7

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

Additional: ADC_IN7

 

 

PB1

 

 

14

 

 

I/O

 

Default: PB1

Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5)

Additional: ADC_IN9

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VSS

15

P

 

Default: VSS

VDD

16

P

 

Default: VDD

 

PA9

 

17

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL

 

PA10

 

18

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

I2C0_SDA

 

PA13

 

19

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PA14

 

20

 

I/O

 

5VT

Default: PA14

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

BOOT0

1

I

 

Default: BOOT0

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330F4 devices only.
(4)Functions are available on GD32F330FB/8/6 devices.
(5)Functions are available on GD32F330FB/8 devices.
 

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 84 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 128 Kbytes of Flash memory
Up to 16 Kbytes of SRAM with hardware parity checking

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash and 16 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. Table 2-2. GD32F330xx memory map shows the memory map of the GD32F330xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 84 MHz/42 MHz/42 MHz. See Figure 2-7. GD32F330xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15).

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, LVD output and USART wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.86 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage (VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx,x=1,2) and the advanced timer (TIMER0) with internal connection. The temperature

sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

DMA

7 channel DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 55 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 55 general purpose I/O pins (GPIO) in GD32F330xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push- pull, open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

One 16-bit advanced timer (TIMER0), one 32-bit general timer (TIMER1) and five 16-bit general timers (TIMER2, TIMER13 ~ TIMER16)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match

Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The GD32F330xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month

automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to two SPI interfaces with a frequency of up to 21 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to two USARTs with operating frequency up to 5.25 MB/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP64 (GD32F330Rx), LQFP48 (GD32F330Cx), QFN32 (GD32F330Kx), QFN28 (GD32F330Gx) and TSSOP20 (GD32F330Fx)
Operation temperature range: -40°C to +85°C (industrial level)
Operation temperature range: -20°C to +85°C (commercial level)

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雷达传感器摄像头视频复合障碍物检测识别防撞探测系统

雷达传感器摄像头视频复合障碍物检测识别防撞探测系统,普通公共交通工具有地铁、公交、轻轨等,由于其不排放SO2等有毒尾气等有害气体的优点,在国内许多城市交通建设部门受到青睐。为保证行车安全,电车一般都是在马路中间行驶,在人行横道与拐弯处有必要采取保护措施。作为一种比较成熟的产品,毫米波雷达的检测性能十分稳定,对环境要求不高,即使在雨雪天气下,它也能很好地工作。其功能主要是对目标距离的测量,对目标的速度和方位进行测量。除功能多样外,毫米波雷达在其它方面也有其优势。比如,它的结构很简单,利用新的RF收发芯片,很快就能形成一套完整的系统;由于工作频率的关系,毫米波雷达发射功率很小,并且可以达到很高的分辨率和灵敏度;与此同时,它的天线可以做的非常小,在主动防撞系统中,毫米波雷达传感器已经成为必然的选择。经实践检验,雷达系统存在人和车不能检测的问题,因此该系统增加了视频设备对近距离行人、单车和车辆的探测预警。 电车雷达视频复合防撞系统是利用雷达传感器和视频传感器联合检测列车行驶前障碍物,评估其危害程度,给出相应的等级预警信号。它具有检测有轨车前障碍物、危险预警和实现与车信号系统控制主机网络通讯等功能。它主要由雷达传感器、雷达系统主机、视频传感器、视频系统主机、防撞障碍物视频融合系统组成。障碍防撞系统主要包括雷达系统和视频系统,它是对远距离车辆目标的跟踪预警,以及视频系统对近距离目标的探测预警。 雷达系统构成障碍物防撞雷达系统由雷达传感器、数据处理模块、电源模块、线缆、安装架和系统软件组成,其中数据处理模块和电源模块采用一体化设计构成系统主机。视频系统构成视频系统,由视频传感器、摄像单元、数据转换和供电模块组成,其中包含镜头和视频处理模块,摄象机对视频数据进行采集和处理,数据转换和供电模块负责视频系统的供电,以及视频系统和雷达主机之间的数据传输功能。 采用毫米波雷达传感器FMCW体制实现了对障碍物的探测与识别,通过两次多收天线方式,可有效地检测多个目标参数。雷达法是利用障碍物反射电磁波现象来发现和确定目标位置的。该方案将障碍物探测雷达安装在有轨电车上,工作于24GHz毫米波段,采用FM连续波测量障碍物距离,并采用数字波束形成技术进行目标定位。接受波束形成器利用n个接收天线阵元构成的天线阵列,接收波束形成技术将多个接收天线所接收的信号合成一个波束。综合的信号在接收波束增强时,通过相位补偿确定波束方向,并根据所需接收回波信号,通过相位补偿确定波束角,可以接收到所需的回波信号。所以起到了空间滤波作用。该接收天线具有较高的灵敏度,能够检测到每一个接收波束在空间辐射范围内具有与多个接收波束相同的微弱信号,因此从技术实现上来说,与多波束收发相比,多波束接收更容易实现,且易于处理,故采用宽波束、多波束接收方式。该雷达安装在有轨电车上,其天线采用两次多接收方式,可进行短距离和远距离混合测量。近距离测量采用宽波束,雷达的方位角50°,垂直波束角4°,探测距离60m;远距离测量采用窄波束,雷达的方位角20°,垂直波束角4°,探测距离200m。窄波束主要用于捕捉远距离目标,帮助驾驶员及时发现目标,并有足够的反应时间,可以有效地避免有轨电车在通过交叉路口时,由于某些突发事件而造成的交通事故。宽频雷达波束主要捕获车头近区域内视觉盲区不易察觉的近距目标,从而避免有轨电车发生一系列因盲区而引起的碰撞事故。 通过距离-多普勒二维回波处理,实现目标距离、速度信息的一体化测量,改进数据处理的实时性,提高信号处理累积增益,从而有效地提高雷达传感器系统对目标的检测灵敏度,是解决多目标识别问题的一种有效方法。多普勒处理方法利用锯齿形调频连续波信号,通过采集多个循环的数据获取平均值,并以每个周期的实际值减去该平均值,可有效地抑制固定杂波的部分,从而简化了后续信号处理。在复杂环境下,该算法还可实现运动目标的距离和速度的去耦合。雷达波形采用锯齿波线性调频连续波,该雷达信号由单扫频信号构成,每一周期仅有一个调频斜率,即信号频率在一个周期内先逐渐升高,到设定值后迅速降至初始值,循环重复。这类信号对于现有的信号发生器来说是比较容易产生的,因此在现代雷达系统中得到了更广泛的应用。 视频近距探测系统雷达传感器视频复合防撞系统视频系统采用成熟的产品。它主要应用于对近距离目标的前方避碰预警(FCW)和行人碰撞预警(PCW)。录像机的摄像是非广角拍摄,拍摄角度有限,因此需要将摄像机安装在距离中轴线左右两侧15cm以内,同时安装位置应尽量不遮挡司机视线。在雷达视频复合防撞系统中,由视频采集器的主机过滤,然后与雷达发出的报警信息融合,输出预警信息,对有轨电车驾驶员发出警告信息,避免碰撞。 雷达传感器限界内障碍物检测识别障碍物探测系统能在有轨电车运行限界内探测到目标、距离、速度、利用现代数字滤波器,根据其运动特性(近/远)的运动特性,对目标轨迹进行测向计算,再利用现代数字滤波器预测它的运动轨迹。计算评价有轨电车目标移动速度和制动特性时,对电车危险程度进行评定。静态指标。在限界内要识别静态目标,并移除有轨。动态目标。在限界内,动态目标应该按照其运动轨迹进行危险度评价。障碍检测系统不能误报、漏报前方障碍。 雷达传感器限界外障碍物检测识别障碍物探测系统,能在有轨电车在运行过程中探测到目标,测速、测速、方位,然后用现代数字滤波跟踪预测有轨电车的轨迹。通过运动特征(接近/远离等)、到电车的距离、目标物的速度、电车的速度、制动特性,计算出其对电车的危险程度。静态指标。在限制范围外,应该去掉静态目标。动态目标。在限定范围外,需要确定动态目标,并根据其运动轨迹判断是否有害。 坡道、弯道障碍物检测识别障碍物检测系统根据线路数据和列车定位信息,识别出当前的列车坡道、弯道路况等线路状态。 (1)斜坡。对于上、下坡道道路,障碍物检测系统需要分析线路坡度等情况,并进行障碍物报警识别,不能因为上、下坡道的误报或漏报。 (2)弯曲。障碍物检测系统在弯道路况下,对弯道转弯半径等线路状况进行分析,调整线路限界,并进行障碍物报警识别,避免误报和误报。 平交路口障碍物检测识别障碍检测系统根据线路数据和列车定位信息,判断列车当前位置是否是平交口。对于交叉路口的路况,障碍物检测系统需要考虑前方车辆较多和车头近距盲区的情况,调整探测分析和预警算法,对障碍物进行报警识别,不应因平交路口造成误报或漏报。 多级预警功能障碍探测系统可以检测32个障碍物的距离、方位及移动障碍物的轨迹。该系统的处理中心根据检测信息和电车本身的运动参数,例如列车运行速度等,来确定碰撞可能发生碰撞的位置和预计碰撞的时间,识别前方障碍物的危险等级,并将危险目标实时传送到车载设备上。依据电车紧急制动速率,常用制动速率将预警情况分为三种,分别为有碰撞危险、有无可避免碰撞的可能性。如果障碍物检测系统检测到障碍物有碰撞危险,就会发出警报。火车在靠近障碍物位置或可能发生碰撞的地点时,系统判定列车极有可能发生碰撞,应及时采取常规的制动措施。并且当列车接近于障碍物位置或可能发生碰撞的地点时,系统判定为无法避免的碰撞,必须采取紧急制动措施。 视频系统功能(1)正面防撞。发出警告音的声音是在与前车有可能发生碰撞之前的2.7秒内;警报声是一连串的高声蜂鸣声。(2)低转速防撞。警告音可能是在与前车低速相撞之前发出警告声;在30km/h以下的时速,以一系列短促的高音量蜂鸣声报警。(3)行人躲避碰撞。在经过车辆前行的道路时,行人发出警报;只有当日间车速低于50km/h时才启动;在昏暗或夜间,系统不能工作;报警声是一连串高音蜂鸣声。气候、光照等因素会对视频系统的识别和反应能力产生很大影响,如部分或完全阻隔视觉传感器的视野,将导致视频系统功能的丧失或减弱。 障碍防撞雷达视频组合系统为有轨电车运行提供辅助安全预警功能,提示可能出现的危险;雷达传感器和录像设备虽然已应用到相关领域的先进创新技术,但是仍然无法保证百分之一百的准确探测车辆和行人,因此无法保证提供所有相应的声音警告。由于道路、道路设施、天气等因素都会对系统识别和反应能力产生很大影响,因此,应继续遵循安全驾驶规范和安全驾驶惯例,并辅以该系统的使用。
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03
2021-12

以gd芯片代理商GD32为基础制造业实现智能化通用变频方案GD集成栅极驱动器赋能电动工具应用

发布时间: : 2021-12--03
以gd芯片代理商GD32为基础制造业实现智能化通用变频方案GD集成栅极驱动器赋能电动工具应用,以GD32F303为基础,支持制造业实现智能化改造,通用变频方案设计。2020年9月,我国确定了碳达峰和2060年碳中和的目标,今后40年内实现碳减排净零排放对中国来说将是一项艰巨的任务。对电动机行业而言,电机在工业领域占据着重要地位,据统计,我国电机年消耗电力总量的69%和工业用电总量的75%左右。所以降低电机寿命中的碳排放,加快电机减碳过程是电机工业面临的重要课题。变频器技术能够正确地控制交流电动机的转速,使其处于节能状态,是对传统电动机系统进行调速,提高电动机系统运行效率的关键措施。常规变频器具有体积大、性能低、价格高等特点,另外对环境也有一定要求,对于分散控制的场合,传统变频器很难满足工业应用的需要。 本文以以gd芯片代理商GD32MCU为核心的VF/矢量变频器控制系统,采用模块化设计,控制面板,用户界面可根据需要自由组合,安装方便.编程及初始化设计,容易实现异步电机调速要求。结合总线技术,可以方便地与控制系统.集散系统相连,实现计算机驱动系统控制和工厂车间集中控制。所以本变频器在汽车、食品、物料输送.工业控制等智能制造领域有着广阔的应用空间。 方案特点: 设计内核采用GD32F303RCT6控制,使系统结构简单、易于实现、成本低、可靠性高。系统在优化硬件结构的同时,不降低系统性能,硬件系统模块清晰、直观,便于安装使用和程序初始化。采用SVPWM控制技术,可以有效地降低逆变器输出电压谐波成份,提高电压利用率,提高控制精度。 以gd芯片代理商GD32F303介绍: 1、Cortex®-M4内核@120MHz。 2、软件和硬件支持DSP指令。 3、flash存取为0等待。 4、内建256KB到3072KB的闪存。 5、内装48KB到96KBSRAM。 6、EXMC接口支持外部SDRAM。 7、多达5个UART(9Mbit/s) 8、多达3个SPI(30Mbit/s) 9、多达2个I2C(400Kbit/s) 10、多可达到2CAN2.0B。 11、I2S的高值是2。 12、SDIO.EthernetMAC支持。 13、USBOTGFS支持。 14、高达3个12位,2.6MSPSADC(多达24路) 15、多达为2DAC。 16、备用电流是2毫安。 关键的控制原则与实施: 该调制器具有线性范围宽、高次谐少、易实现数字化等特点,广泛应用于异步电动机。MOS管在传统的三相桥驱动电路中有8种开关组合,即000.001.010.011.100.101.110.111。000.111是零向量。6个非零基压空间矢量把αβ平面分成6个扇区。通过对8个基本空间电压矢量作用时间的控制,得出了各基本空间电压矢量作用时间及输出次序,获得圆周旋转磁场。 TIMER0模块是以gd芯片代理商GD32中的一个增强型定时器模块,天生用于电机控制,可产生3组6路PWM,每组2路PWM可作为互补,并可带死区使用,可用于驱动H桥。用三通道TIM0模块产生总共6路PWM输出。以下是详细的步骤: 打开TIM0时钟,将相应的IO口设置为多路输出。 将TIM0设定为ARR和PSC,当TIM0打开时钟后,设定ARR和PSC两个寄存器的值,以控制输出PWM的周期。 为TIM0_CH0.TIM0_CH1.TIM0_CH2设置PWM模式。 通过TIM0的CH0~CH2输出,使能量达到TIM0。 修正TIM0_CCR1~TIM0_CCR2以控制占空比。 利用上述配置,配合GD32F303运算能力,实时调整占空比,达到矢量控制效果。 赋能型电动工具应用GD30DR8306高集成栅极驱动器,电气工具是以电为动力的各种通用构造器具,一般还是依靠工人手工操作,广泛用于建筑装修、轻工制造等领域。与纯人工手工工具相比,电动工具通过电力大幅度提高工具的扭力.转速.冲击力等,大大提高工作效率。普通电动工具有电钻.电动砂轮机.电动扳手.电动螺丝刀.电锤.电钻.混凝土振动器.电刨等。根据等级,电动工具可以分为专业级、工用级和通用级。 1、根据市场规模,2020年全球电动工具市场约为360亿美元,2025年约为460亿美元,而2017年CAGR约为5.3%。 2、从市场细分来看,专业级以上电动工具占商业用途的比重为63.2%,相对于一般居民用途的30.8%,这种结构在较长时期内将保持基本稳定。 3、从区域市场上看,2019年北美市场份额.亚太市场份额与欧洲份额持平,分别为30.8%.28.7%和28.6,另外11.9%的地区,如拉美非洲,这类结构同样也将保持相对稳定,到2025年,亚太地区将略升至31.1%。 以gd芯片代理商GD30DR8306驱动器主要特性: GD30DR8306是三相栅极驱动器,带有可选的DC/DC降压控制器。所述芯片包含三个半桥驱动器,每个驱动器可以驱动两个NMOSFET,并支持大的拉电流和1A的灌流能力。根据应用中所用功率MOSFET的不同,驱动电流会自动调节。专用转换率控制用于降低栅极驱动EMI值。GD30DR8306可以在4.5V到30V单电源下工作。这个装置与一个支持100%占空比的可调节电荷泵相结合,从而提供门极驱动电流和内部LDO。 1、电压4.5-30V宽压供电; 2、可编程序的门极驱动电流,峰值1A灌流和1.2A拉电流; 3、智能化的高端低端压摆控制; 4、PWM输入控制高可达200kHz; 5、可选择2个PWM模式(6x和3x); 6、内置5V/2ADC-DC电压降控制器; 7、3.3V和5V数字接口; 8、整合5VLDO; 9、散热增强:QFN32(5x5); 10、保护职能: --死区时间插入; --MOSFET直通保护; --过温保护; --故障诊断; --VDD欠压闭锁(UVLO); 成功案例: GD32F303+GD30DR8306。 配置1650中空杯型无刷马达。 电源电压:锂电池7.4V,锂电池11.1V。 速度:100~30000rpm。 控制模式:无霍尔FOC/无霍尔方波。 这个方案的主要特征: 1、所用的以gd芯片代理商GD30DR8306驱动芯片将3个开关二极管集成在一起,例如IN4148,1个5VLDO,1个DC-DCBuck控制器,使得外围电路元件大大减少,节省了PCB空间,降低了BOM成本。 2、使用完全的NMOSFET,一致性好,稳定性好。与传统的P+NMOSFET电路设计相比,由于PMOSFET和NMOSFET的Rdson阻值有较大差别,PMOSFET的管道速度比N慢,在弦波控制/或方波调速时很难做到均衡。 3、利用FOC算法控制中空杯无感电机,具有良好的动态性、低噪声、高效率、长寿命及良好的使用体验。
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