这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F330G8U6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F330G8U6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F330xx ARM® Cortex®-M4 32-bit MCU Datasheet General description The GD32F330xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support. The GD32F330xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 84 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, up to five general 16-bit timers, a general 32-bit timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F330xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.   Part Number GD32F330xx   F4 F6 F8 G4 G6 G8 K4 K6 K8 C4 C6 C8 CB R8 RB Flash Code area (KB)   16   32   64   16   32   64   16   32   64   16   32   64   64   64   64   Data area (KB)   0   0   0   0   0   0   0   0   0   0   0   0   64   0   64   Total (KB) 16 32 64 16 32 64 16 32 64 16 32 64 128 64 128 SRAM (KB) 4 4 8 4 4 8 4 4 8 4 4 8 16 16 16 Timers Genaral timer (32-bit) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1)   Genaral timer (16-bit) 4 (2,13,15,16) 4 (2,13,15,16) 4 (2,13,15,16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 4 (2,13,15,16) 4 (2,13,15,16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16)   Advanced timer (16-bit) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0)   SysTick 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F330G8U6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F330xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

General description

The GD32F330xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support.
The GD32F330xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 84 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, up to five general 16-bit timers, a general 32-bit timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F330xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.

 

Part Number

GD32F330xx

 

F4

F6

F8

G4

G6

G8

K4

K6

K8

C4

C6

C8

CB

R8

RB

Flash

Code area

(KB)

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

64

 

64

 

64

 

Data area

(KB)

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

64

 

0

 

64

 

Total (KB)

16

32

64

16

32

64

16

32

64

16

32

64

128

64

128

SRAM (KB)

4

4

8

4

4

8

4

4

8

4

4

8

16

16

16

Timers

Genaral timer

(32-bit)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

 

Genaral timer

(16-bit)

4

(2,13,15,16)

4

(2,13,15,16)

4

(2,13,15,16)

4

(2,13,15,16)

4

(2,13,15,16)

5

(2,13-16)

4

(2,13,15,16)

4

(2,13,15,16)

5

(2,13-16)

4

(2,13,15,16)

4

(2,13,15,16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

 

Advanced

timer (16-bit)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

 

SysTick

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Connectivity

 

USART

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

 

 

I2C

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

 

 

SPI

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

2

(0-1)

GPIO

15

15

15

23

23

23

27

27

27

39

39

39

39

55

55

EXTI

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

ADC

Units

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Channels

(External)

9

9

9

10

10

10

10

10

10

10

10

10

10

16

16

 

Channels

(Internal)

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

Package

TSSOP20

QFN28

QFN32

LQFP48

LQFP64

 

Memory map

Table 2-2. GD32F330xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0xE000 0000 - 0xE00F FFFF

Cortex-M4 internal peripherals

External Device

 

0xA000 0000 - 0xDFFF FFFF

Reserved

External RAM

 

0x6000 0000 - 0x9FFF FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripherals

 

AHB1

0x5004 0000 - 0x5FFF FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

Reserved

 

 

 

 

 

AHB2

0x4800 1800 - 0x4FFF FFFF

Reserved

 

 

0x4800 1400 - 0x4800 17FF

GPIOF

 

 

0x4800 1000 - 0x4800 13FF

Reserved

 

 

0x4800 0C00 - 0x4800 0FFF

GPIOD

 

 

0x4800 0800 - 0x4800 0BFF

GPIOC

 

 

0x4800 0400 - 0x4800 07FF

GPIOB

 

 

0x4800 0000 - 0x4800 03FF

GPIOA

 

 

 

 

 

 

 

AHB1

0x4002 4400 - 0x47FF FFFF

Reserved

 

 

0x4002 4000 - 0x4002 43FF

Reserved

 

 

0x4002 3400 - 0x4002 3FFF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1400 - 0x4002 1FFF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0400 - 0x4002 0FFF

Reserved

 

 

0x4002 0000 - 0x4002 03FF

DMA

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 8000 - 0x4001 FFFF

Reserved

 

 

0x4001 5C00 - 0x4001 7FFF

Reserved

 

 

0x4001 4C00 - 0x4001 5BFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER16

 

 

0x4001 4400 - 0x4001 47FF

TIMER15

 

 

0x4001 4000 - 0x4001 43FF

TIMER14

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

Reserved

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

Reserved

 

 

0x4001 2400 - 0x4001 27FF

ADC

 

 

0x4001 0800 - 0x4001 23FF

Reserved

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 0000 - 0x4001 03FF

SYSCFG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

CTC

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

Reserved

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6400 - 0x4000 6FFF

Reserved

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 4800 - 0x4000 53FF

Reserved

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

Reserved

 

 

0x4000 3800 - 0x4000 3BFF

SPI1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1400 - 0x4000 1FFF

Reserved

 

 

0x4000 1000 - 0x4000 13FF

Reserved

 

 

0x4000 0800 - 0x4000 0FFF

Reserved

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

SRAM

 

0x2000 4000 - 0x3FFF FFFF

Reserved

 

 

0x2000 0000 - 0x2000 3FFF

SRAM

 

 

 

 

Code

 

0x1FFF FC00 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF FBFF

Option bytes

 

 

0x1FFF EC00 - 0x1FFF F7FF

System memory

 

 

0x0802 0000 - 0x1FFF EBFF

Reserved

 

 

0x0800 0000 - 0x0801 FFFF

Main Flash memory

 

 

0x0010 0000 - 0x07FF FFFF

Reserved

 

 

0x0000 0000 - 0x000F FFFF

Aliased to Flash or system memory

 

GD32F330Rx LQFP64 pin definitions

Table 2-3. GD32F330Rx LQFP64 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13- TAMPER-

RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

PF0-OSCIN

 

5

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1- OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

 

PC0

 

8

 

I/O

 

Default: PC0

Alternate: EVENTOUT Additional: ADC_IN10

 

PC1

 

9

 

I/O

 

Default: PC1

Alternate: EVENTOUT Additional: ADC_IN11

 

PC2

 

10

 

I/O

 

Default: PC2 Alternate: EVENTOUT

Additional: ADC_IN12

 

PC3

 

11

 

I/O

 

Default: PC3

Alternate: EVENTOUT Additional: ADC_IN13

VSSA

12

P

 

Default: VSSA

VDDA

13

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

14

 

 

I/O

 

Default: PA0

Alternate: USART1_CTS, TIMER1_CH0, TIMER1_ETI, I2C1_SCL

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

PA1

 

 

15

 

 

I/O

 

Default: PA1

Alternate: USART1_RTS, TIMER1_CH1, I2C1_SDA, EVENTOUT

Additional: ADC_IN1

 

PA2

 

16

 

I/O

 

Default: PA2

Alternate: USART1_TX, TIMER1_CH2, TIMER14_CH0

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Additional: ADC_IN2

 

 

 

 

Default: PA3

PA3

17

I/O

 

Alternate: USART1_RX, TIMER1_CH3, TIMER14_CH1

 

 

 

 

Additional: ADC_IN3

 

PF4

 

18

 

I/O

 

5VT

Default: PF4

Alternate: EVENTOUT

 

PF5

 

19

 

I/O

 

5VT

Default: PF5

Alternate: EVENTOUT

 

 

 

 

Default: PA4

PA4

20

I/O

 

Alternate: SPI0_NSS, USART1_CK, TIMER13_CH0,

SPI1_NSS

 

 

 

 

Additional: ADC_IN4

 

 

 

 

Default: PA5

PA5

21

I/O

 

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

 

 

 

 

Additional: ADC_IN5

 

 

 

 

Default: PA6

PA6

22

I/O

 

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN,

TIMER15_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

PA7

23

I/O

 

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,

TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PC4

PC4

24

I/O

 

Alternate: EVENTOUT

 

 

 

 

Additional: ADC_IN14

 

PC5

 

25

 

I/O

 

Default: PC5

Additional: ADC_IN15, WKUP4

 

 

 

 

Default: PB0

PB0

26

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

27

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK

 

 

 

 

Additional: ADC_IN9

PB2

28

I/O

5VT

Default: PB2

 

PB10

 

29

 

I/O

 

5VT

Default: PB10

Alternate: I2C1_SCL, TIMER1_CH2, SPI1_IO2

 

 

 

 

Default: PB11

PB11

30

I/O

5VT

Alternate:I2C1_SDA, TIMER1_CH3, EVENTOUT,

 

 

 

 

SPI1_IO3

VSS

31

P

 

Default: VSS

VDD

32

P

 

Default: VDD

PB12

33

I/O

5VT

Default: PB12

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: SPI1_NSS, TIMER0_BKIN, I2C1_SMBA,

 

 

 

 

EVENTOUT

 

PB13

 

34

 

I/O

 

5VT

Default: PB13

Alternate: SPI1_SCK, TIMER0_CH0_ON

 

 

 

 

Default: PB14

PB14

35

I/O

5VT

Alternate: SPI1_MISO, TIMER0_CH1_ON,

 

 

 

 

TIMER14_CH0

 

 

 

 

Default: PB15

 

PB15

 

36

 

I/O

 

5VT

Alternate: SPI1_MOSI, TIMER0_CH2_ON,

TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

PC6

 

37

 

I/O

 

5VT

Default: PC6

Alternate: TIMER2_CH0

 

PC7

 

38

 

I/O

 

5VT

Default: PC7

Alternate: TIMER2_CH1

 

PC8

 

39

 

I/O

 

5VT

Default: PC8

Alternate: TIMER2_CH2

 

PC9

 

40

 

I/O

 

5VT

Default: PC9

Alternate: TIMER2_CH3

 

 

 

 

Default: PA8

PA8

41

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX, EVENTOUT,CTC_SYNC

 

 

 

 

Default: PA9

PA9

42

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,

 

 

 

 

I2C0_SCL

 

 

 

 

Default: PA10

PA10

43

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

I2C0_SDA

 

 

 

 

Default: PA11

PA11

44

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,

 

 

 

 

SPI1_IO2

 

 

 

 

Default: PA12

PA12

45

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,

 

 

 

 

SPI1_IO3

 

PA13

 

46

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO

 

PF6

 

47

 

I/O

 

5VT

Default: PF6

Alternate: I2C1_SCL

 

PF7

 

48

 

I/O

 

5VT

Default: PF7

Alternate: I2C1_SDA

 

PA14

 

49

 

I/O

 

5VT

Default: PA14

Alternate: USART1_TX, SWCLK, SPI1_MOSI

 

 

 

 

Default: PA15

PA15

50

I/O

5VT

Alternate: SPI0_NSS , USART1_RX, TIMER1_CH0,

 

 

 

 

TIMER1_ETI, SPI1_NSS, EVENTOUT

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PC10

51

I/O

5VT

Default: PC10

PC11

52

I/O

5VT

Default: PC11

PC12

53

I/O

5VT

Default: PC12

 

PD2

 

54

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI

 

PB3

 

55

 

I/O

 

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

 

PB4

 

56

 

I/O

 

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

PB5

 

 

57

 

 

I/O

 

 

5VT

Default: PB5

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1

Additional:WKUP5

 

PB6

 

58

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

 

PB7

 

59

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

60

I

 

Default: BOOT0

 

PB8

 

61

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

 

PB9

 

62

 

I/O

 

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0,

EVENTOUT

VSS

63

P

 

Default: VSS

VDD

64

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330C4 devices only.
(4)Functions are available on GD32F330CB/8/6 devices.
(5)Functions are available on GD32F330CB/8 devices.

GD32F330Cx LQFP48 pin definitions

Table 2-4. GD32F330Cx LQFP48 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13-

TAMPER- RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

 

 

 

Default: PF0

PF0-OSCIN

5

I/O

5VT

Alternate: CTC_SYNC

 

 

 

 

Additional: OSCIN

PF1-

OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

VSSA

8

P

 

Default: VSSA

VDDA

9

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

10

I/O

 

Alternate: USART0_CTS(3), USART1_CTS(4),

TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

 

 

 

 

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

 

 

Default: PA1

PA1

11

I/O

 

Alternate: USART0_RTS(3), USART1_RTS(4),

TIMER1_CH1, I2C1_SDA(5), EVENTOUT

 

 

 

 

Additional: ADC_IN1

 

 

 

 

Default: PA2

PA2

12

I/O

 

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,

TIMER14_CH0

 

 

 

 

Additional: ADC_IN2

 

 

 

 

Default: PA3

PA3

13

I/O

 

Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3,

TIMER14_CH1

 

 

 

 

Additional: ADC_IN3

 

 

 

 

Default: PA4

PA4

14

I/O

 

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),

TIMER13_CH0, SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4

 

 

 

 

Default: PA5

PA5

15

I/O

 

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

 

 

 

 

Additional: ADC_IN5

 

 

 

 

Default: PA6

PA6

16

I/O

 

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN,

TIMER15_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

PA7

17

I/O

 

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,

TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

18

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PB1

PB1

19

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

PB2

20

I/O

5VT

Default: PB2

 

 

 

 

Default: PB10

PB10

21

I/O

5VT

Alternate: I2C0_SCL(3),I2C1_SCL(5), TIMER1_CH2,

 

 

 

 

SPI1_IO2(5)

 

 

 

 

Default: PB11

PB11

22

I/O

5VT

Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3,

 

 

 

 

EVENTOUT, SPI1_IO3(5)

VSS

23

P

 

Default: VSS

VDD

24

P

 

Default: VDD

 

 

 

 

Default: PB12

PB12

25

I/O

5VT

Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN,

 

 

 

 

I2C1_SMBA(5), EVENTOUT

 

PB13

 

26

 

I/O

 

5VT

Default: PB13

Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON

 

 

 

 

Default: PB14

PB14

27

I/O

5VT

Alternate: SPI0_MISO(3), SPI1_MISO(5),

 

 

 

 

TIMER0_CH1_ON, TIMER14_CH0

 

 

 

 

Default: PB15

 

PB15

 

28

 

I/O

 

5VT

Alternate: SPI0_MOSI(3), SPI1_MOSI(5),

TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

 

 

 

Default: PA8

PA8

29

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,CTC_SYNC

 

 

 

 

Default: PA9

PA9

30

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,

 

 

 

 

I2C0_SCL

 

 

 

 

Default: PA10

PA10

31

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

I2C0_SDA

 

 

 

 

Default: PA11

PA11

32

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,

 

 

 

 

SPI1_IO2(5)

 

 

 

 

Default: PA12

PA12

33

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,

 

 

 

 

SPI1_IO3(5)

 

PA13

 

34

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PF6

 

35

 

I/O

 

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PF7

36

I/O

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

 

PA14

 

37

 

I/O

 

5VT

Default: PA14

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

 

PA15

 

38

 

I/O

 

5VT

Default: PA15

Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT

PB3

39

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

PB4

40

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

PB5

 

 

41

 

 

I/O

 

 

5VT

Default: PB5

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1

Additional:WKUP5

 

PB6

 

42

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

PB7

43

I/O

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

44

I

 

Default: BOOT0

PB8

45

I/O

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

 

PB9

 

46

 

I/O

 

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0,

EVENTOUT

VSS

47

P

 

Default: VSS

VDD

48

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330C4 devices only.
(4)Functions are available on GD32F330CB/8/6 devices.
(5)Functions are available on GD32F330CB/8 devices.

GD32F330Kx QFN32 pin definitions

Table 2-5. GD32F330Kx QFP32 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0

Alternate: CTC_SYNC Additional: OSCIN

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

PF1-

OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

 

 

Default: PA0

PA0-WKUP

6

I/O

 

Alternate: USART0_CTS(3), USART1_CTS(4),

TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

 

 

 

 

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

 

 

Default: PA1

PA1

7

I/O

 

Alternate: USART0_RTS(3), USART1_RTS(4),

TIMER1_CH1, I2C1_SDA(5), EVENTOUT

 

 

 

 

Additional: ADC_IN1

 

 

 

 

Default: PA2

PA2

8

I/O

 

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,

TIMER14_CH0

 

 

 

 

Additional: ADC_IN2

 

 

 

 

Default: PA3

PA3

9

I/O

 

Alternate: USART0_RX(3), USART1_RX(4),

TIMER1_CH3, TIMER14_CH1

 

 

 

 

Additional: ADC_IN3

 

 

 

 

Default: PA4

PA4

10

I/O

 

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),

TIMER13_CH0, SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4

 

 

 

 

Default: PA5

PA5

11

I/O

 

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

 

 

 

 

Additional: ADC_IN5

 

 

 

 

Default: PA6

PA6

12

I/O

 

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN,

TIMER15_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

PA7

13

I/O

 

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,

TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

14

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

15

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

PB2

16

I/O

5VT

Default: PB2

VDD

17

P

 

Default: VDD

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PA8

 

18

 

I/O

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT,CTC_SYNC

 

PA9

 

19

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL

 

PA10

 

20

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

I2C0_SDA

 

PA11

 

21

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT, SPI1_IO2(5)

 

PA12

 

22

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5)

 

PA13

 

23

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PA14

 

24

 

I/O

 

5VT

Default: PA14

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

 

PA15

 

25

 

I/O

 

5VT

Default: PA15

Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT

PB3

26

I/O

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

PB4

27

I/O

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

PB5

 

 

28

 

 

I/O

 

 

5VT

Default: PB5

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1

Additional:WKUP5

PB6

29

I/O

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

 

PB7

 

30

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

31

I

 

Default: BOOT0

PB8

32

I/O

5VT

Default: PB8

Alternate: I2C0_SCL, TIMER15_CH0

VDD

1

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330K4 devices only.
(4)Functions are available on GD32F330KB/8/6 devices.

(5)Functions are available on GD32F330KB/8 devices.

GD32F330Gx QFN28 pin definitions

Table 2-6. GD32F330Gx QFN28 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1- OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

6

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

PA1

 

 

7

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1

 

 

PA2

 

 

8

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0

Additional: ADC_IN2

 

 

PA3

 

 

9

 

 

I/O

 

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1

Additional: ADC_IN3

 

 

PA4

 

 

10

 

 

I/O

 

Default: PA4

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Additional: ADC_IN4

 

PA5

 

11

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

Additional: ADC_IN5

 

 

PA6

 

 

12

 

 

I/O

 

Default: PA6

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT

Additional: ADC_IN6

 

 

PA7

 

 

13

 

 

I/O

 

Default: PA7

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

Additional: ADC_IN7

 

PB0

 

14

 

I/O

 

Default: PB0

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

USART1_RX, EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

15

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

VSS

16

P

 

Default: VSS

VDD

17

P

 

Default: VDD

 

 

 

 

Default: PA8

PA8

18

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX, EVENTOUT,CTC_SYNC

 

 

 

 

Default: PA9

PA9

19

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,

 

 

 

 

I2C0_SCL

 

 

 

 

Default: PA10

PA10

20

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

I2C0_SDA

 

PA13

 

21

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

 

 

 

Default: PA14

PA14

22

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

23

I/O

5VT

Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4),

 

 

 

 

TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT

 

PB3

 

24

 

I/O

 

5VT

Default: PB3

Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT

 

PB4

 

25

 

I/O

 

5VT

Default: PB4

Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT

 

 

 

 

Default: PB5

PB5

26

I/O

5VT

Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN,

TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

PB6

 

27

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON

 

PB7

 

28

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON

BOOT0

1

I

 

Default: BOOT0

 

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330G4 devices only.
(4)Functions are available on GD32F330GB/8/6 devices.
(5)Functions are available on GD32F330GB/8 devices.

GD32F330Fx TSSOP20 pin definitions

Table 2-7. GD32F330Fx TSSOP20 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0

Alternate: CTC_SYNC Additional: OSCIN

PF1- OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

6

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5)

Additional: ADC_IN0, RTC_TAMP1, WKUP0

 

 

PA1

 

 

7

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1

 

 

PA2

 

 

8

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0

Additional: ADC_IN2

 

 

PA3

 

 

9

 

 

I/O

 

Default: PA3

Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1

Additional: ADC_IN3

 

 

PA4

 

 

10

 

 

I/O

 

Default: PA4

Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)

Additional: ADC_IN4

 

PA5

 

11

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI

Additional: ADC_IN5

 

 

PA6

 

 

12

 

 

I/O

 

Default: PA6

Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT

Additional: ADC_IN6

 

 

PA7

 

 

13

 

 

I/O

 

Default: PA7

Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT

Additional: ADC_IN7

 

 

PB1

 

 

14

 

 

I/O

 

Default: PB1

Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5)

Additional: ADC_IN9

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VSS

15

P

 

Default: VSS

VDD

16

P

 

Default: VDD

 

PA9

 

17

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL

 

PA10

 

18

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

I2C0_SDA

 

PA13

 

19

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PA14

 

20

 

I/O

 

5VT

Default: PA14

Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5)

BOOT0

1

I

 

Default: BOOT0

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F330F4 devices only.
(4)Functions are available on GD32F330FB/8/6 devices.
(5)Functions are available on GD32F330FB/8 devices.
 

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 84 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 128 Kbytes of Flash memory
Up to 16 Kbytes of SRAM with hardware parity checking

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash and 16 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. Table 2-2. GD32F330xx memory map shows the memory map of the GD32F330xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 84 MHz/42 MHz/42 MHz. See Figure 2-7. GD32F330xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15).

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, LVD output and USART wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.86 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage (VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx,x=1,2) and the advanced timer (TIMER0) with internal connection. The temperature

sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

DMA

7 channel DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 55 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 55 general purpose I/O pins (GPIO) in GD32F330xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push- pull, open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

One 16-bit advanced timer (TIMER0), one 32-bit general timer (TIMER1) and five 16-bit general timers (TIMER2, TIMER13 ~ TIMER16)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match

Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The GD32F330xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month

automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to two SPI interfaces with a frequency of up to 21 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to two USARTs with operating frequency up to 5.25 MB/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP64 (GD32F330Rx), LQFP48 (GD32F330Cx), QFN32 (GD32F330Kx), QFN28 (GD32F330Gx) and TSSOP20 (GD32F330Fx)
Operation temperature range: -40°C to +85°C (industrial level)
Operation temperature range: -20°C to +85°C (commercial level)

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14
2022-01

微波雷达传感器雷达感应浴室镜上的应用

发布时间： : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用，如今，家用电器的智能化已成为一种常态，越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入，今天就来说说这个话题。 什么是智能浴室镜？智慧型浴室镜，顾名思义，就是卫浴镜子智能化升级，入门级产品基本具备了彩灯和镜面触摸功能，更高档次的产品安装有微波雷达传感器智能感应，当感应到有人接近到一定距离即可开启亮灯或者亮屏操作，也可三色无极调，智能除雾，语音交互，日程安排备忘，甚至在镜子上看电视，听音乐，气象预报，问题查询，智能控制，健康管理等。 智能化雷达感应浴室镜与普通镜的区别，为什么要选TA？，就功能而言，普通浴镜价格用它没有什么压力！而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言，普通浴镜功能单一，而微波雷达传感器智能浴室镜功能创新：镜子灯光色温和亮度可以自由调节，镜面还可以湿手触控，智能除雾，既环保又健康！ 尽管智能浴镜比较新颖，但功能丰富，体验感更好，特别是入门级的智能浴镜，具有基础智能化功能，真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么？ ①确定智能浴室镜的安装位置，因为是安装时在墙壁上打孔，一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时，根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后，在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度，一般智能浴镜的标准安装高度约85cm(从地砖到镜子底)，具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍，可用酒精或30%清洁稀释液擦洗，平时可用干毛巾养护，注意多通风。
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07
2022-02

冰箱屏幕唤醒微波雷达传感器屏幕唤醒性能强悍智能感应

发布时间： : 2022-02--07
冰箱屏幕唤醒微波雷达传感器屏幕唤醒性能强悍智能感应，随着年轻一代消费观念的转变，冰箱作为厨房和客厅的核心家用电器之一，也升级为健康、智能、高端的形象。在新产品发布会上，推出了大屏幕的冰箱，不仅屏幕优秀，而且微波雷达传感器屏幕唤醒性能强大。 大屏智能互联，听歌看剧购物新体验 冰箱植入冰箱屏幕唤醒微波雷达传感器触摸屏，重新定义了冰箱的核心价值。除了冰箱的保鲜功能外，该显示屏还集控制中心、娱乐中心和购物中心于一体，让您在无聊的烹饪过程中不会落后于听歌、看剧和购物。新的烹饪体验是前所未有的。 不仅如此，21.5英寸的屏幕也是整个房子智能互联的互动入口。未来的家将是一个充满屏幕的家。冰箱可以通过微波雷达传感器屏幕与家庭智能产品连接。烹饪时，你可以通过冰箱观看洗衣机的工作，当你不能腾出手来照顾孩子时，你可以通过冰箱屏幕连接家庭摄像头，看到孩子的情况。冰箱的推出标志着屏幕上的未来之家正在迅速到来。 管理RFID食材，建立健康的家庭生活 据报道，5G冰箱配备了RFID食品材料管理模块，用户将自动记录和储存食品，无需操作。此外，冰箱还可以追溯食品来源，监控食品材料从诞生到用户的整个过程，以确保食品安全；当食品即将过期时，冰箱会自动提醒用户提供健康的饮食和生活。 风冷无霜，清新无痕 冰箱的出现是人类延长食品保存期的一项伟大发明。一个好的冰箱必须有很强的保存能力。5g冰箱采用双360度循环供气系统。智能补水功能使食品原料享受全方位保鲜，紧紧锁住水分和营养，防止食品原料越来越干燥。此外，该送风系统可将其送到冰箱的每个角落，消除每个储藏空间的温差，减少手工除霜的麻烦，使食品不再粘连。 进口电诱导保鲜技术，创新黑科技加持 针对传统冰箱保存日期不够长的痛点，5g互联网冰箱采用日本进口电诱导保存技术，不仅可以实现水果储存冰箱2周以上不腐烂发霉，还可以使蔬菜储存25天不发黄、不起皱。在-1℃~-5℃下，配料不易冻结，储存时间较长。冷冻食品解冻后无血，营养大化。此外，微波雷达传感器5g冰箱还支持-7℃~-24℃的温度调节，以满足不同配料的储存要求。 180°矢量变频，省电时更安静 一台好的压缩机对冰箱至关重要。冰箱配备了变频压缩机。180°矢量变频技术可根据冷藏室和冷冻室的需要有效提供冷却，达到食品原料的保鲜效果。180°矢量变频技术不仅大大降低了功耗，而且以非常低的分贝操作机器。保鲜效果和节能安静的技术冰箱可以在许多智能冰箱中占有一席之地，仅仅通过这种搭配就吸引了许多消费者的青睐。 配备天然草本滤芯，不再担心串味 各种成分一起储存在冰箱中，难以避免串味。此外，冰箱内容易滋生细菌，冰箱总是有异味。针对这一问题，冰箱创新配置了天然草本杀菌除臭滤芯。该滤芯提取了多种天然草本活性因子，可有效杀菌99.9%，抑制冰箱异味，保持食材新鲜。不仅如此，这个草本滤芯可以更快、更方便、更无忧地拆卸。家里有冰箱，开始健康保鲜的生活。 目前，冰箱屏幕唤醒微波雷达传感器正在继续推动家庭物联网的快速普及，相信在不久的将来，智能家电将成为互动终端。
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23
2023-03

esp32 c3蓝牙芯片模组上海乐鑫代理商RISC-V处理器内核工具链

发布时间： : 2023-03--23
esp32 c3蓝牙芯片模组上海乐鑫代理商RISC-V处理器内核工具链，自RISC-V 架构诞生以来，市场上已有数十个版本的 RISC-V 内核和 SoC 芯片它们中的一部分是开源免费的，而商业公司开发的 RISC-V 处理器内核和平台是需要商业授权的。某些商业公司开发用于内部使用的 RISC-V 内核，但也可以开源运作。esp32 c3蓝牙芯片模组上海乐鑫代理商介绍到西部数据的SweRV架构(RV32IMC)是 RISC-V 内核处理器的典型代表，它是一个32 bit 顺序执行指令架构，具有双向超标量设计和9级流水线，采用28 nm工艺技术实现，运行频率高达 1.8 GHz，可提供 4.9 CoreMark/MHz 的性能，略高于ARM的 Cortex A15，已经在西部数据的 SSD 和HDD 控制器上使用，SweRV 项目是一个开源项目(Chip Alliance)。 典型的开源 RISC-V内核有 Roket Core，它是加州大学伯克利分校开发的一个经典的 RV64 设计。伯克利分校还开发了一个 BOOM Core，它与 Rocket Core 不同的是面向更高的性能。苏黎世理工大学(ETH Zurich)开发的 Zero-riscy，是经典的RV32 设计。esp32 c3蓝牙芯片模组上海乐鑫代理商介绍到苏黎世理工大学还开发了另外一款 RISC-V R15CY Core，可配置成RV32E，面向的是超低功耗、超小芯片面积的应用场景。由 Clifford Wolf 开发的RISC-V Core-Pico RV32，其内核重点在于追求面积和 CPU 频率的优化。 开源的 RISC-V 内核非常适用于研究和教学，但用于商业芯片设计还有许多工作要做。SiFive(美国赛科技)由 Yunsup Lee 创立，他也是 RISC-V 的创始人之一。2017 年SiFive 公司发布 RISC-V 内核、SC 平台家族，以及相关支持软件和开发板。esp32 c3蓝牙芯片模组上海乐鑫代理商介绍到在这些芯片中，包括采用 28 nm 制造技术，支持 Linux 操作系统的 64 位多核CPU U500，以及采用180 nm 制造技术的多外设低成本 IOT 处理器内核 E300开发 RISC-V处理器内核的厂商还包括 Codasip、Syntacore、T-Head(平头哥半导体)、Andes (晶芯科技)，以及创业公司芯来科技等。 RISC-V GNU 工具链 RISC-V GNU工具链包括 riscv gcc 编译器、riscv binutils 链接器汇编器、riscv gdb GDB调试工具以及 OpenOCD 。 OpenOCD(Open 0n-Chip Debugger，开源片上调试器)是一款开源的调试软件，它提供针对人式设备的调试、系统编程和边界扫描功能。esp32 c3蓝牙芯片模组上海乐鑫代理商介绍到OpenOCD需要硬件仿真器来配合完成调试。例如 J-Link或者CMSIS-DAP等。OpenOCD内置了 GDB server模块，可以通过 GDB命令来调试硬件。 目前，市场上支持 RISC-V 处理器开源的 GNU 工具软件有 SiFive Freedo Sudio、AndesSight 和 Nuclei tudio IDE。这些软件针对自家企业 RISC-V 处内核开发和优化，集成开发环境基于开源的 Eclipse。 如果开发者有兴趣，完全可以自己下载以下几个开源软件搭建一个 RISC-V发环境。esp32 c3蓝牙芯片模组上海乐鑫代理商介绍到这些软件是jdk-8ul01-windows-x64.exe、Eclipse IDE for C/C++ develoners，GNU MCU Eclipse Windows Build Tools、OpenOCD 以及 risev32-unknown-elf-gcc。
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