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兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F405RGT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F405RGT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F405xx ARM® Cortex®-M4 32-bit MCU Datasheet Introduction The GD32F405xx device belongs to the connectivity line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F405xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 192 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and two UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS. Additional peripherals as Digital camera interface (DCI) is included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F405xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on. Device information Table 1. GD32F405xx devices features and peripheral list   Part Number GD32F405xx   RE RG RK VG VK VG VK ZG ZK Flash Code Area (KB) 512 512 512 512 512 512 512 512 512   Data Area (KB) 0 512 2560 512 2560 512 2560 512 2560   Total (KB) 512 1024 3072 1024 3072 1024 3072 1024 3072 SRAM (KB) 192 192 192 192 192 192 192 192 192 Timers 16-bit GPTM 8 8 8 8 8 8 8 8 8   32-bit GPTM 2 2 2 2 2 2 2 2 2   Adv. 16-bit TM 2 2 2 2 2 2 2 2 2   Basic TM 2 2 2 2 2 2 2 2 2   SysTick 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 1 Connectivity USART+UART 4+2 4+2 4+2 4+2 4+2 4+2 4+2 4+2 4+2   I2C 3 3 3 3 3 3 3 3 3   SPI/I2S 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2   SDIO 1 1 1
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F405RGT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F405xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

Introduction

The GD32F405xx device belongs to the connectivity line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support.
The GD32F405xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 192 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and two UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS. Additional peripherals as Digital camera interface (DCI) is included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications.
The above features make GD32F405xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on.

Device information

Table 1. GD32F405xx devices features and peripheral list

 

Part Number

GD32F405xx

 

RE

RG

RK

VG

VK

VG

VK

ZG

ZK

Flash

Code Area (KB)

512

512

512

512

512

512

512

512

512

 

Data Area (KB)

0

512

2560

512

2560

512

2560

512

2560

 

Total (KB)

512

1024

3072

1024

3072

1024

3072

1024

3072

SRAM (KB)

192

192

192

192

192

192

192

192

192

Timers

16-bit GPTM

8

8

8

8

8

8

8

8

8

 

32-bit GPTM

2

2

2

2

2

2

2

2

2

 

Adv. 16-bit TM

2

2

2

2

2

2

2

2

2

 

Basic TM

2

2

2

2

2

2

2

2

2

 

SysTick

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

USART+UART

4+2

4+2

4+2

4+2

4+2

4+2

4+2

4+2

4+2

 

I2C

3

3

3

3

3

3

3

3

3

 

SPI/I2S

3/2

3/2

3/2

3/2

3/2

3/2

3/2

3/2

3/2

 

SDIO

1

1

1

1

1

1

1

1

1

 

CAN 2.0B

2

2

2

2

2

2

2

2

2

 

USB OTG

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

 

Digital Camera

1

1

1

1

1

1

1

1

1

GPIO

51

51

51

82

82

82

82

114

114

ADC Unit (CHs)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(24)

3(24)

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP64

LQFP100

BGA100

LQFP144

Memory map

Figure 6. GD32F405xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

External Device

 

 

 

AHB

matrix

0xC000 0000 - 0xDFFF FFFF

EXMC - SDRAM

 

 

0xA000 1000 - 0xBFFF FFFF

Reserved

 

 

0xA000 0000 - 0xA000 0FFF

Reserved

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

Reserved

 

 

0x7000 0000 - 0x8FFF FFFF

Reserved

 

 

0x6000 0000 - 0x6FFF FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

AHB2

0x5006 0C00 - 0x5FFF FFFF

Reserved

 

 

0x5006 0800 - 0x5006 0BFF

TRNG

 

 

0x5005 0400 - 0x5006 07FF

Reserved

 

 

0x5005 0000 - 0x5005 03FF

DCI

 

 

0x5004 0000 - 0x5004 FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB1

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

USBHS

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

Reserved

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

DMA1

 

 

0x4002 6000 - 0x4002 63FF

DMA0

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

BKPSRAM

 

 

0x4002 3C00 - 0x4002 3FFF

FMC

 

 

0x4002 3800 - 0x4002 3BFF

RCU

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

GPIOI

 

 

0x4002 1C00 - 0x4002 1FFF

GPIOH

 

 

0x4002 1800 - 0x4002 1BFF

GPIOG

 

 

0x4002 1400 - 0x4002 17FF

GPIOF

 

 

0x4002 1000 - 0x4002 13FF

GPIOE

 

 

0x4002 0C00 - 0x4002 0FFF

GPIOD

 

 

0x4002 0800 - 0x4002 0BFF

GPIOC

 

 

0x4002 0400 - 0x4002 07FF

GPIOB

 

 

0x4002 0000 - 0x4002 03FF

GPIOA

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 6C00 - 0x4001 FFFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5800 - 0x4001 67FF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

Reserved

 

 

0x4001 5000 - 0x4001 53FF

Reserved

 

 

0x4001 4C00 - 0x4001 4FFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER10

 

 

0x4001 4400 - 0x4001 47FF

TIMER9

 

 

0x4001 4000 - 0x4001 43FF

TIMER8

 

 

0x4001 3C00 - 0x4001 3FFF

EXTI

 

 

0x4001 3800 - 0x4001 3BFF

SYSCFG

 

 

0x4001 3400 - 0x4001 37FF

Reserved

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

SDIO

 

 

0x4001 2400 - 0x4001 2BFF

Reserved

 

 

0x4001 2000 - 0x4001 23FF

ADC

 

 

0x4001 1800 - 0x4001 1FFF

Reserved

 

 

0x4001 1400 - 0x4001 17FF

USART5

 

 

0x4001 1000 - 0x4001 13FF

USART0

 

 

0x4001 0800 - 0x4001 0FFF

Reserved

 

 

0x4001 0400 - 0x4001 07FF

TIMER7

 

 

0x4001 0000 - 0x4001 03FF

TIMER0

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 C800 - 0x4000 FFFF

Reserved

 

 

0x4000 C400 - 0x4000 C7FF

IVREF

 

 

0x4000 8000 - 0x4000 C3FF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

CTC

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

I2C2

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 4000 - 0x4000 43FF

I2S2_add

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

I2S1_add

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

SRAM

 

 

AHB

matrix

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2003 0000 - 0x2006 FFFF

Reserved

 

 

0x2002 0000 - 0x2002 FFFF

Reserved

 

 

0x2001 C000 - 0x2001 FFFF

SRAM1(16KB)

 

 

0x2000 0000 - 0x2001 BFFF

SRAM0(112KB)

 

 

 

 

 

 

 

 

Code

 

 

 

 

 

 

 

 

AHB

matrix

0x1FFF C010 - 0x1FFF FFFF

Reserved

 

 

0x1FFF C000 - 0x1FFF C00F

Option bytes(Bank 0)

 

 

0x1FFF 7A10 - 0x1FFF BFFF

Reserved

 

 

0x1FFF 7800 - 0x1FFF 7A0F

OTP(528B)

 

 

0x1FFF 0000 - 0x1FFF 77FF

Boot loader(30KB)

 

 

0x1FFE C010 - 0x1FFE FFFF

Reserved

 

 

0x1FFE C000 - 0x1FFE C00F

Option bytes(Bank 1)

 

 

0x1001 0000 - 0x1FFE BFFF

Reserved

 

 

0x1000 0000 - 0x1000 FFFF

TCMSRAM(64KB)

 

 

0x0830 0000 - 0x0FFF FFFF

Reserved

 

 

0x0800 0000 - 0x082F FFFF

Main Flash(3072KB)

 

 

 

0x0000 0000 - 0x07FF FFFF

Aliased to

the boot device

Pin definitions

Table 2. GD32F405xx pin definitions

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PE2

 

B2

 

1

 

1

 

-

 

I/O

 

5VT

Default: PE2

Alternate: TRACECLK, EVENTOUT

 

PE3

 

A1

 

2

 

2

 

-

 

I/O

 

5VT

Default: PE3

Alternate:TRACED0, EVENTOUT

 

PE4

 

B1

 

3

 

3

 

-

 

I/O

 

5VT

Default: PE4

Alternate:TRACED1, DCI_D4, EVENTOUT

 

PE5

 

C2

 

4

 

4

 

-

 

I/O

 

5VT

Default: PE5

Alternate:TRACED2,TIMER8_CH0, DCI_D6, EVENTOUT

 

PE6

 

D2

 

5

 

5

 

-

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3,TIMER8_CH1, DCI_D7, EVENTOUT

VBAT

E2

6

6

1

P

-

Default: VBAT

PC13- TAMPER-

RTC

 

C1

 

7

 

7

 

2

 

I/O

 

5VT

Default: PC13 Alternate: EVENTOUT

Additional: RTC_TAMP0, RTC_OUT, RTC_TS

 

PC14- OSC32IN

 

D1

 

8

 

8

 

3

 

I/O

 

5VT

Default: PC14

Alternate: EVENTOUT Additional: OSC32IN

 

PC15- OSC32OUT

 

E1

 

9

 

9

 

4

 

I/O

 

5VT

Default: PC15

Alternate: EVENTOUT Additional: OSC32OUT

 

PF0

 

-

 

10

 

-

 

-

 

I/O

 

5VT

Default: PF0

Alternate:I2C1_SDA, EVENTOUT, CTC_SYNC

 

PF1

 

-

 

11

 

-

 

-

 

I/O

 

5VT

Default: PF1

Alternate: I2C1_SCL, EVENTOUT

 

PF2

 

-

 

12

 

-

 

-

 

I/O

 

5VT

Default: PF2

Alternate: I2C1_SMBA, EVENTOUT

 

PF3

 

-

 

13

 

-

 

-

 

I/O

 

5VT

Default: PF3

Alternate: EVENTOUT, I2C1_TXFRAME

Additional: ADC2_IN9

 

PF4

 

-

 

14

 

-

 

-

 

I/O

 

5VT

Default: PF4 Alternate: EVENTOUT

Additional: ADC2_IN14

 

PF5

 

-

 

15

 

-

 

-

 

I/O

 

5VT

Default: PF5 Alternate: EVENTOUT

Additional: ADC2_IN15

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

VSS

F2

16

10

-

P

-

Default: VSS

VDD

G2

17

11

-

P

-

Default: VDD

 

PF6

 

-

 

18

 

-

 

-

 

I/O

 

5VT

Default: PF6 Alternate:TIMER9_CH0, EVENTOUT

Additional: ADC2_IN4

 

PF7

 

-

 

19

 

-

 

-

 

I/O

 

5VT

Default: PF7 Alternate:TIMER10_CH0, EVENTOUT

Additional: ADC2_IN5

 

PF8

 

-

 

20

 

-

 

-

 

I/O

 

5VT

Default: PF8

Alternate: TIMER12_CH0, EVENTOUT Additional: ADC2_IN6

 

PF9

 

-

 

21

 

-

 

-

 

I/O

 

5VT

Default: PF9

Alternate: TIMER13_CH0, EVENTOUT Additional: ADC2_IN7

 

PF10

 

-

 

22

 

-

 

-

 

I/O

 

5VT

Default: PF10

Alternate: DCI_D11, EVENTOUT Additional: ADC2_IN8

 

PH0

 

F1

 

23

 

12

 

5

 

I/O

 

5VT

Default: PH0, OSCIN Alternate: EVENTOUT

Additional: OSCIN

 

PH1

 

G1

 

24

 

13

 

6

 

I/O

 

5VT

Default: PH1, OSCOUT Alternate: EVENTOUT

Additional: OSCOUT

NRST

H2

25

14

7

-

-

Default: NRST

 

PC0

 

H1

 

26

 

15

 

8

 

I/O

 

5VT

Default: PC0

Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10

 

PC1

 

J2

 

27

 

16

 

9

 

I/O

 

5VT

Default: PC1

Alternate:SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT

Additional: ADC012_IN11

 

PC2

 

J3

 

28

 

17

 

10

 

I/O

 

5VT

Default: PC2 Alternate:SPI1_MISO,I2S1_ADD_SD,USBHS_ULPI_DIR, EVENTOUT

Additional: ADC012_IN12

 

PC3

 

K2

 

29

 

18

 

11

 

I/O

 

5VT

Default: PC3 Alternate:SPI1_MOSI,I2S1_SD,USBHS_ULPI_NXT, EVENTOUT

Additional: ADC012_IN13

VDD

-

30

19

-

P

-

Default: VDD

VSSA

J1

31

20

12

P

-

Default: VSSA

VREFN

K1

-

-

-

P

-

Default: VREF-

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

VREFP

L1

32

21

-

P

-

Default: VREF+

VDDA

M1

33

22

13

P

-

Default: VDDA

 

 

PA0-WKUP

 

 

L2

 

 

34

 

 

23

 

 

14

 

 

I/O

 

 

5VT

Default: PA0 Alternate:TIMER1_CH0,TIMER1_ETI,TIMER4_CH0, TIMER7_ETI,USART1_CTS, UART3_TX, EVENTOUT

Additional: ADC012_IN0, WKUP

 

 

PA1

 

 

M2

 

 

35

 

 

24

 

 

15

 

 

I/O

 

 

5VT

Default: PA1

Alternate:TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT

Additional: ADC012_IN1

 

 

PA2

 

 

K3

 

 

36

 

 

25

 

 

16

 

 

I/O

 

 

5VT

Default: PA2 Alternate:TIMER1_CH2,TIMER4_CH2,TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT

Additional: ADC012_IN2

 

 

PA3

 

 

L3

 

 

37

 

 

26

 

 

17

 

 

I/O

 

 

5VT

Default: PA3 Alternate:TIMER1_CH3,TIMER4_CH3,TIMER8_CH1, I2S1_MCK,USART1_RX,USBHS_ULPI_D0, EVENTOUT

Additional: ADC012_IN3

VSS

-

38

27

18

P

-

Default: VSS

NC

E3

-

-

-

-

-

-

VDD

-

39

28

19

P

-

Default: VDD

 

 

PA4

 

 

M3

 

 

40

 

 

29

 

 

20

 

 

I/O

 

 

TTa

Default: PA4

Alternate:SPI0_NSS,SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, EVENTOUT

Additional: ADC01_IN4, DAC_OUT0

 

 

PA5

 

 

K4

 

 

41

 

 

30

 

 

21

 

 

I/O

 

 

TTa

Default: PA5

Alternate:TIMER1_CH0,TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT

Additional: ADC01_IN5, DAC_OUT1

 

 

PA6

 

 

L4

 

 

42

 

 

31

 

 

22

 

 

I/O

 

 

5VT

Default: PA6 Alternate:TIMER0_BRKIN,TIMER2_CH0,TIMER7_BRKIN,SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT

Additional: ADC01_IN6

 

 

PA7

 

 

M4

 

 

43

 

 

32

 

 

23

 

 

I/O

 

 

5VT

Default: PA7 Alternate:TIMER0_CH0_ON,TIMER2_CH1,

TIMER7_CH0_ON,SPI0_MOSI,TIMER13_CH0, EVENTOUT

Additional: ADC01_IN7

 

PC4

 

K5

 

44

 

33

 

24

 

I/O

 

5VT

Default: PC4

Alternate: EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

 

 

 

 

 

 

Additional: ADC01_IN14

 

PC5

 

L5

 

45

 

34

 

25

 

I/O

 

5VT

Default: PC5

Alternate:USART2_RX, EVENTOUT Additional: ADC01_IN15

 

 

PB0

 

 

M5

 

 

46

 

 

35

 

 

26

 

 

I/O

 

 

5VT

Default: PB0 Alternate:TIMER0_CH1_ON,TIMER2_CH2,TIMER7_CH1_ON,SPI2_MO SI,I2S2_SD,USBHS_ULPI_D1, SDIO_D1, EVENTOUT

Additional: ADC01_IN8, IREF

 

 

PB1

 

 

M6

 

 

47

 

 

36

 

 

27

 

 

I/O

 

 

5VT

Default: PB1 Alternate:TIMER0_CH2_ON,TIMER2_CH3,TIMER7_CH2_ON,USBHS_ ULPI_D2, SDIO_D2, EVENTOUT

Additional: ADC01_IN9

 

PB2

 

L6

 

48

 

37

 

28

 

I/O

 

5VT

Default: PB2, BOOT1 Alternate:TIMER1_CH3,SPI2_MOSI,I2S2_SD,USBHS_ULPI_D4,

SDIO_CK, EVENTOUT

 

PF11

 

-

 

49

 

-

 

-

 

I/O

 

5VT

Default: PF11

Alternate: DCI_D12, EVENTOUT

 

PF12

 

-

 

50

 

-

 

-

 

I/O

 

5VT

Default: PF12

Alternate: EVENTOUT

VSS

-

51

-

-

P

-

Default: VSS

VDD

-

52

-

-

P

-

Default: VDD

 

PF13

 

-

 

53

 

-

 

-

 

I/O

 

5VT

Default: PF13

Alternate: EVENTOUT

 

PF14

 

-

 

54

 

-

 

-

 

I/O

 

5VT

Default: PF14

Alternate: EVENTOUT

 

PF15

 

-

 

55

 

-

 

-

 

I/O

 

5VT

Default: PF15

Alternate: EVENTOUT

 

PG0

 

-

 

56

 

-

 

-

 

I/O

 

5VT

Default: PG0

Alternate: EVENTOUT

 

PG1

 

-

 

57

 

-

 

-

 

I/O

 

5VT

Default: PG1

Alternate: EVENTOUT

 

PE7

 

M7

 

58

 

38

 

-

 

I/O

 

5VT

Default: PE7

Alternate: TIMER0_ETI, EVENTOUT

 

PE8

 

L7

 

59

 

39

 

-

 

I/O

 

5VT

Default: PE8

Alternate: TIMER0_CH0_ON, EVENTOUT

 

PE9

 

M8

 

60

 

40

 

-

 

I/O

 

5VT

Default: PE9

Alternate: TIMER0_CH0, EVENTOUT

VSS

-

61

-

-

P

-

Default: VSS

VDD

-

62

-

-

P

-

Default: VDD

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PE10

 

L8

 

63

 

41

 

-

 

I/O

 

5VT

Default: PE10

Alternate: TIMER0_CH1_ON, EVENTOUT

 

PE11

 

M9

 

64

 

42

 

-

 

I/O

 

5VT

Default: PE11

Alternate:TIMER0_CH1, EVENTOUT

 

PE12

 

L9

 

65

 

43

 

-

 

I/O

 

5VT

Default: PE12

Alternate:TIMER0_CH2_ON, EVENTOUT

 

PE13

 

M10

 

66

 

44

 

-

 

I/O

 

5VT

Default: PE13

Alternate:TIMER0_CH2, EVENTOUT

 

PE14

 

M11

 

67

 

45

 

-

 

I/O

 

5VT

Default: PE14

Alternate:TIMER0_CH3, EVENTOUT

 

PE15

 

M12

 

68

 

46

 

-

 

I/O

 

5VT

Default: PE15

Alternate: TIMER0_BRKIN, EVENTOUT

 

PB10

 

L10

 

69

 

47

 

29

 

I/O

 

5VT

Default: PB10

Alternate:TIMER1_CH2,I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK,USART2_TX,USBHS_ULPI_D3, SDIO_D7, EVENTOUT

 

PB11

 

K9

 

70

 

48

 

30

 

I/O

 

5VT

Default: PB11

Alternate:TIMER1_CH3,I2C1_SDA,I2S_CKIN,USART2_RX,USBHS_UL PI_D4, EVENTOUT

NC

L11

71

49

31

P

-

Default: VCORE

VSS

F12

-

-

-

P

-

Default: VSS

VDD

G12

72

50

32

P

-

Default: VDD

 

PB12

 

L12

 

73

 

51

 

33

 

I/O

 

5VT

Default: PB12 Alternate:TIMER0_BRKIN,I2C1_SMBA,SPI1_NSS, I2S1_WS,

USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT

 

 

 

PB13

 

 

 

K12

 

 

 

74

 

 

 

52

 

 

 

34

 

 

 

I/O

 

 

 

5VT

Default: PB13 Alternate:TIMER0_CH0_ON,SPI1_SCK,I2S1_CK, USART2_CTS,CAN1_TX,USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME

Additional: USBHS_VBUS

 

PB14

 

K11

 

75

 

53

 

35

 

I/O

 

5VT

Default: PB14 Alternate:TIMER0_CH1_ON,TIMER7_CH1_ON,SPI1_MISO,I2S1_ADD_

SD,USART2_RTS,TIMER11_CH0,USBHS_DM, EVENTOUT

 

PB15

 

K10

 

76

 

54

 

36

 

I/O

 

5VT

Default: PB15 Alternate:RTC_REFIN,TIMER0_CH2_ON,TIMER7_CH2_ON,

SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT

 

PD8

 

-

 

77

 

55

 

-

 

I/O

 

5VT

Default: PD8

Alternate: USART2_TX, EVENTOUT

 

PD9

 

K8

 

78

 

56

 

-

 

I/O

 

5VT

Default: PD9

Alternate: USART2_RX, EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PD10

 

J12

 

79

 

57

 

-

 

I/O

 

5VT

Default: PD10

Alternate: USART2_CK, EVENTOUT

 

PD11

 

J11

 

80

 

58

 

-

 

I/O

 

5VT

Default: PD11

Alternate: USART2_CTS, EVENTOUT

 

PD12

 

J10

 

81

 

59

 

-

 

I/O

 

5VT

Default: PD12

Alternate:TIMER3_CH0,USART2_RTS , EVENTOUT

 

PD13

 

H12

 

82

 

60

 

-

 

I/O

 

5VT

Default: PD13

Alternate: TIMER3_CH1, EVENTOUT

VSS

-

83

-

-

P

-

Default: VSS

VDD

-

84

-

-

P

-

Default: VDD

 

PD14

 

H11

 

85

 

61

 

-

 

I/O

 

5VT

Default: PD14

Alternate: TIMER3_CH2, EVENTOUT

 

PD15

 

H10

 

86

 

62

 

-

 

I/O

 

5VT

Default: PD15

Alternate:TIMER3_CH3, EVENTOUT, CTC_SYNC

 

PG2

 

-

 

87

 

-

 

-

 

I/O

 

5VT

Default: PG2

Alternate: EVENTOUT

 

PG3

 

-

 

88

 

-

 

-

 

I/O

 

5VT

Default: PG3

Alternate: EVENTOUT

 

PG4

 

-

 

89

 

-

 

-

 

I/O

 

5VT

Default: PG4

Alternate: EVENTOUT

 

PG5

 

-

 

90

 

-

 

-

 

I/O

 

5VT

Default: PG5

Alternate: EVENTOUT

 

PG6

 

-

 

91

 

-

 

-

 

I/O

 

5VT

Default: PG6

Alternate: DCI_D12, EVENTOUT

 

PG7

 

-

 

92

 

-

 

-

 

I/O

 

5VT

Default: PG7

Alternate:USART5_CK, DCI_D13, EVENTOUT

 

PG8

 

-

 

93

 

-

 

-

 

I/O

 

5VT

Default: PG8

Alternate:USART5_RTS, EVENTOUT

VSS

-

94

-

-

P

-

Default: VSS

VDD

-

95

-

-

P

-

Default: VDD

 

PC6

 

E12

 

96

 

63

 

37

 

I/O

 

5VT

Default: PC6 Alternate:TIMER2_CH0,TIMER7_CH0,I2S1_MCK,USART5_TX,

SDIO_D6, DCI_D0, EVENTOUT

 

PC7

 

E11

 

97

 

64

 

38

 

I/O

 

5VT

Default: PC7

Alternate:TIMER2_CH1,TIMER7_CH1,SPI1_SCK,I2S1_CK,I2S2_MCK, USART5_RX,SDIO_D7,DCI_D1,EVENTOUT

 

PC8

 

E10

 

98

 

65

 

39

 

I/O

 

5VT

Default: PC8

Alternate:TRACED0,TIMER2_CH2,TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PC9

 

D12

 

99

 

66

 

40

 

I/O

 

5VT

Default: PC9 Alternate:CK_OUT1,TIMER2_CH3,TIMER7_CH3,I2C2_SDA, I2S_CKIN,

SDIO_D1, DCI_D3, EVENTOUT

 

PA8

 

D11

 

100

 

67

 

41

 

I/O

 

5VT

Default: PA8 Alternate:CK_OUT0,TIMER0_CH0,I2C2_SCL,USART0_CK,

USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC

 

 

PA9

 

 

D10

 

 

101

 

 

68

 

 

42

 

 

I/O

 

 

5VT

Default: PA9 Alternate:TIMER0_CH1,I2C2_SMBA,SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT

Additional: USBFS_VBUS

 

PA10

 

C12

 

102

 

69

 

43

 

I/O

 

5VT

Default: PA10 Alternate:TIMER0_CH2,USART0_RX,USBFS_ID,DCI_D1, EVENTOUT,

I2C2_TXFRAME

 

PA11

 

B12

 

103

 

70

 

44

 

I/O

 

5VT

Default: PA11 Alternate:TIMER0_CH3,USART0_CTS,USART5_TX,CAN0_RX,

USBFS_DM, EVENTOUT

 

PA12

 

A12

 

104

 

71

 

45

 

I/O

 

5VT

Default: PA12 Alternate:TIMER0_ETI,USART0_RTS,USART5_RX, CAN0_TX,

USBFS_DP, EVENTOUT

 

PA13

 

A11

 

105

 

72

 

46

 

I/O

 

5VT

Default: JTMS, SWDIO, PA13

Alternate: EVENTOUT

NC

C11

106

73

47

-

-

-

VSS

F11

107

74

-

P

-

Default: VSS

VDD

G11

108

75

48

P

-

Default: VDD

 

PA14

 

A10

 

109

 

76

 

49

 

I/O

 

5VT

Default: JTCK, SWCLK, PA14

Alternate: EVENTOUT

 

PA15

 

A9

 

110

 

77

 

50

 

I/O

 

5VT

Default: JTDI, PA15

Alternate:TIMER1_CH0,TIMER1_ETI,SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT

 

PC10

 

B11

 

111

 

78

 

51

 

I/O

 

5VT

Default: PC10

Alternate:SPI2_SCK,I2S2_CK,USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT

 

PC11

 

C10

 

112

 

79

 

52

 

I/O

 

5VT

Default: PC11 Alternate:I2S2_ADD_SD,SPI2_MISO,USART2_RX, UART3_RX,

SDIO_D3, DCI_D4, EVENTOUT

 

PC12

 

B10

 

113

 

80

 

53

 

I/O

 

5VT

Default: PC12 Alternate:I2C1_SDA,SPI2_MOSI,I2S2_SD,USART2_CK, UART4_TX,

SDIO_CK, DCI_D9, EVENTOUT

PD0

C9

114

81

-

I/O

5VT

Default: PD0

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

 

 

 

 

 

 

Alternate:SPI2_MOSI, I2S2_SD, CAN0_RX, EVENTOUT

 

PD1

 

B9

 

115

 

82

 

-

 

I/O

 

5VT

Default: PD1

Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EVENTOUT

 

PD2

 

C8

 

116

 

83

 

54

 

I/O

 

5VT

Default: PD2

Alternate:TIMER2_ETI,UART4_RX,SDIO_CMD,DCI_D11, EVENTOUT

 

PD3

 

B8

 

117

 

84

 

-

 

I/O

 

5VT

Default: PD3

Alternate:TRACED1,SPI1_SCK,I2S1_CK, USART1_CTS, DCI_D5,EVENTOUT

 

PD4

 

B7

 

118

 

85

 

-

 

I/O

 

5VT

Default: PD4

Alternate: USART1_RTS, EVENTOUT

 

PD5

 

A6

 

119

 

86

 

-

 

I/O

 

5VT

Default: PD5

Alternate: USART1_TX, EVENTOUT

VSS

-

120

-

-

P

-

Default: VSS

VDD

-

121

-

-

P

-

Default: VDD

 

PD6

 

B6

 

122

 

87

 

-

 

I/O

 

5VT

Default: PD6

Alternate:SPI2_MOSI,I2S2_SD,USART1_RX, DCI_D10, EVENTOUT

 

PD7

 

A5

 

123

 

88

 

-

 

I/O

 

5VT

Default: PD7

Alternate:USART1_CK, EVENTOUT

 

PG9

 

-

 

124

 

-

 

-

 

I/O

 

5VT

Default: PG9

Alternate:USART5_RX, DCI_VSYNC, EVENTOUT

 

PG10

 

-

 

125

 

-

 

-

 

I/O

 

5VT

Default: PG10

Alternate: DCI_D2,EVENTOUT

 

PG11

 

-

 

126

 

-

 

-

 

I/O

 

5VT

Default: PG11

Alternate: DCI_D3, EVENTOUT

 

PG12

 

-

 

127

 

-

 

-

 

I/O

 

5VT

Default: PG12

Alternate: USART5_RTS, EVENTOUT

 

PG13

 

-

 

128

 

-

 

-

 

I/O

 

5VT

Default: PG13

Alternate:TRACED2, USART5_CTS, EVENTOUT

 

PG14

 

-

 

129

 

-

 

-

 

I/O

 

5VT

Default: PG14

Alternate:TRACED3, USART5_TX, EVENTOUT

VSS

-

130

-

-

P

-

Default: VSS

VDD

-

131

-

-

P

-

Default: VDD

 

PG15

 

-

 

132

 

-

 

-

 

I/O

 

5VT

Default: PG15

Alternate:USART5_CTS,DCI_D13, EVENTOUT

 

PB3

 

A8

 

133

 

89

 

55

 

I/O

 

5VT

Default: JTDO, PB3 Alternate:TRACESWO,TIMER1_CH1,SPI0_SCK,SPI2_SCK, I2S2_CK,

USART0_RX, I2C1_SDA, EVENTOUT

 

PB4

 

A7

 

134

 

90

 

56

 

I/O

 

5VT

Default: NJTRST, PB4

Alternate:TIMER2_CH0,SPI0_MISO,SPI2_MISO,

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

 

 

 

 

 

 

I2S2_ADD_SD,I2C2_SDA,SDIO_D0,EVENTOUT, I2C0_TXFRAME

 

PB5

 

C5

 

135

 

91

 

57

 

I/O

 

5VT

Default: PB5

Alternate:TIMER2_CH1,I2C0_SMBA,SPI0_MOSI,SPI2_MOSI,I2S2_SD, CAN1_RX,USBHS_ULPI_D7,ETH_PPS_OUT, DCI_D10, EVENTOUT

 

PB6

 

B5

 

136

 

92

 

58

 

I/O

 

5VT

Default: PB6 Alternate:TIMER3_CH0,I2C0_SCL,USART0_TX,CAN1_TX, DCI_D5,

EVENTOUT

 

PB7

 

B4

 

137

 

93

 

59

 

I/O

 

5VT

Default: PB7

Alternate:TIMER3_CH1,I2C0_SDA,USART0_RX, DCI_VSYNC, EVENTOUT

BOOT0

A4

138

94

60

I/O

5VT

Default: BOOT0

 

PB8

 

A3

 

139

 

95

 

61

 

I/O

 

5VT

Default: PB8

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT

 

PB9

 

B3

 

140

 

96

 

62

 

I/O

 

5VT

Default: PB9

Alternate:TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT

 

PE0

 

C3

 

141

 

97

 

-

 

I/O

 

5VT

Default: PE0

Alternate:TIMER3_ETI, DCI_D2, EVENTOUT

 

PE1

 

A2

 

142

 

98

 

-

 

I/O

 

5VT

Default: PE1

Alternate:TIMER0_CH1_ON, DCI_D3, EVENTOUT

VSS

D3

-

99

63

P

-

Default: VSS

PDR_ON

H3

143

-

-

P

-

Default: PDR_ON

VDD

C4

144

100

64

P

-

Default: VDD

Notes:
1.Type: I = input, O = output, P = power.
2.I/O Level: 5VT = 5 V tolerant.

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 168 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 3072 Kbytes of Flash memory, including code Flash and data Flash
512B of OTP (one-time programmable) memory
192 KB of SRAM

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and

accessed (R/W) at CPU clock speed with zero wait states. Up to 192 Kbytes of inner SRAM is composed of SRAM0 (112KB) and SRAM1 (16KB) that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex®-M4 core. The additional 4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the VDD power supply is down. The Figure of GD32F405xx memory map shows the memory map of the GD32F405xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 168 MHz. The maximum frequency of the two APB domains including APB1 is 42 MHz and APB2 is 84 MHz. See Figure 6 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal 30KB of information blocks for the boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART2, and USB Device FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes.

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.6MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for external battery power supply (VBAT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

Two 12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for DMA1)
Support independent 8, 16, 32-bit memory and peripheral transfer
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO and DCI

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 114 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable

There are up to 140 general purpose I/O pins (GPIO) in GD32F405xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced-control timer (TM0 & TM7), eight 16-bit general-purpose timers (TM2, TM3, TM8 ~ TM13), two 32-bit general-purpose timers (TM1 & TM4) and two 16- bit basic timer (TM5 & TM6)
Up to 4 independent channels of PWM, output compare or input capture for each general- purpose timer (GPTM) and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog and window watchdog)

The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 & TM4 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM2 & TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM9 ~ TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F405xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 32 kHz internal RC and as it operates independently of the main clock, it can operate in deep sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC) and backup registers

Independent binary-coded decimal (BCD) format timer/counter with twenty 32-bit backup registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz (Fast mode)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Up to four USARTs and two UARTs with operating frequency up to 9 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4) are used
to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1 and SPI2
Support either master or slave mode Audio
Sampling frequencies from 8 kHz up to 192 kHz are supported.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32F405xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequencies from 8 kHz to 192 kHz is supported.

Universal serial bus on-the-go full-speed (USB OTG FS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator support crystal-less operation
Internal main PLL for USB CLK compliantly
Internal USB OTG FS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation.

Universal serial bus on-the-go high-speed (USB OTG HS)

One USB device/host/OTG high-speed Interface with frequency up to 480 Mbit/s
An external PHY device connected to the ULPI is required when using in HS mode

USB OTG HS supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller provides ULPI interface for external USB PHY integration and it also contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB
2.0 protocol. HUB connection is supported when USB HS operates at high-speed in host mode. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USB HS and system.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Secure digital input and output card interface (SDIO)

Support SD2.0/SDIO2.0/MMC4.2 host interface

The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.

Digital camera interface (DCI)

Digital video/picture capture
8/10/12/14 data width supported
High transfer efficiency with DMA interface
Video/picture crop supported
Various pixel formats supported including JPEG/YCrCb/RGB
Hard/embedded synchronous signals supported

DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

BGA100 (GDF405VxH), LQFP144 (GD32F405Zx), LQFP100 (GD32F405Vx) and LQFP64 (GD32F405Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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18
2022-02

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

发布时间： : 2022-02--18
uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗，指纹门锁并不是什么新鲜事，我相信每个人都很熟悉。随着近年来智能家居的逐步普及，指纹门锁也进入了成千上万的家庭。今天的功耗雷达模块指纹门锁不仅消除了繁琐的钥匙，而且还提供了各种智能功能，uA级别智能门锁低功耗雷达模块用在智能门锁上，可以实现门锁的智能感应屏幕，使电池寿命延长3-5倍，如与其他智能家居连接，成为智能场景的开关。所以今天的指纹门锁更被称为智能门锁。 今天，让我们来谈谈功耗雷达模块智能门锁的安全性。希望能让更多想知道智能门锁的朋友认识下。 指纹识别是智能门锁的核心 指纹识别技术在我们的智能手机上随处可见。从以前的实体指纹识别到屏幕下的指纹识别，可以说指纹识别技术已经相当成熟。指纹识别可以说是整个uA级低功耗雷达模块智能门锁的核心。 目前主要有三种常见的指纹识别方法，即光学指纹识别、半导体指纹识别和超声指纹识别。 光学指纹识别 让我们先谈谈光学指纹识别的原理实际上是光的反射。我们都知道指纹本身是不均匀的。当光照射到我们的指纹上时，它会反射，光接收器可以通过接收反射的光来绘制我们的指纹。就像激光雷达测绘一样。 光学指纹识别通常出现在打卡机上，手机上的屏幕指纹识别技术也使用光学指纹识别。今天的光学指纹识别已经达到了非常快的识别速度。 然而，光学指纹识别有一个缺点，即硬件上的活体识别无法实现，容易被指模破解。通常，活体识别是通过软件算法进行的。如果算法处理不当，很容易翻车。 此外，光学指纹识别也容易受到液体的影响，湿手解锁的成功率也会下降。 超声指纹识别 超声指纹识别也被称为射频指纹识别，其原理与光学类型相似，但超声波使用声波反射，实际上是声纳的缩小版本。因为使用声波，不要担心水折射会降低识别率，所以超声指纹识别可以湿手解锁。然而，超声指纹识别在防破解方面与光学类型一样，不能实现硬件，可以被指模破解，活体识别仍然依赖于算法。 半导体指纹识别 半导体指纹识别主要采用电容、电场（即我们所说的电感）、温度和压力原理来实现指纹图像的收集。当用户将手指放在前面时，皮肤形成电容阵列的极板，电容阵列的背面是绝缘极板。由于不同区域指纹的脊柱与谷物之间的距离也不同，因此每个单元的电容量随之变化，从而获得指纹图像。半导体指纹识别具有价格低、体积小、识别率高的优点，因此大多数uA级低功耗雷达模块智能门锁都采用了这种方案。半导体指纹识别的另一个功能是活体识别。传统的硅胶指模无法破解。 当然，这并不意味着半导体可以百分识别活体。所谓的半导体指纹识别活体检测不使用指纹活体体征。本质上，它取决于皮肤的材料特性，这意味着虽然传统的硅胶指模无法破解。 一般来说，无论哪种指纹识别，都有可能被破解，只是说破解的水平。然而，今天的指纹识别，无论是硬件生活识别还是算法生活识别，都相对成熟，很难破解。毕竟，都可以通过支付级别的认证，大大保证安全。 目前，市场上大多数智能门锁仍将保留钥匙孔。除了指纹解锁外，用户还可以用传统钥匙开门。留下钥匙孔的主要目的是在指纹识别故障或智能门锁耗尽时仍有开门的方法。但由于有钥匙孔，它表明它可以通过技术手段解锁。 目前市场上的锁等级可分为A、B、C三个等级，这三个等级主要是通过防暴开锁和防技术开锁的程度来区分的。A级锁要求技术解锁时间不少于1分钟，B级锁要求不少于5分钟。即使是高级别的C级锁也只要求技术解锁时间不少于10分钟。 也就是说，现在市场上大多数门锁，无论是什么级别，在专业的解锁大师面前都糊，只不过是时间长短。 安全是重要的，是否安全增加了人们对uA级别低功耗雷达模块智能门锁安全的担忧。事实上，现在到处都是摄像头，强大的人脸识别，以及移动支付的出现，使家庭现金减少，所有这些都使得入室盗窃的成本急剧上升，近年来各省市的入室盗窃几乎呈悬崖状下降。 换句话说，无论锁有多安全，无论锁有多难打开，都可能比在门口安装摄像头更具威慑力。 因此，担心uA级别低功耗雷达模块智能门锁是否不安全可能意义不大。毕竟，家里的防盗锁可能不安全。我们应该更加关注门锁能给我们带来多少便利。 我们要考虑的是智能门锁的兼容性和通用性。毕竟，智能门锁近年来才流行起来。大多数人在后期将普通机械门锁升级为智能门锁。因此，智能门锁能否与原门兼容是非常重要的。如果不兼容，发现无法安装是一件非常麻烦的事情。 uA级别低功耗雷达模块智能门锁主要是为了避免带钥匙的麻烦。因此，智能门锁的便利性尤为重要。便利性主要体现在指纹的识别率上。手指受伤导致指纹磨损或老年人指纹较浅。智能门锁能否识别是非常重要的。 当然，如果指纹真的失效，是否有其他解锁方案，如密码解锁或NFC解锁。还需要注意密码解锁是否有虚假密码等防窥镜措施。 当然，智能门锁的耐久性也是一个需要特别注意的地方。uA级别低功耗雷达模块智能门锁主要依靠内部电池供电，这就要求智能门锁的耐久性尽可能好，否则经常充电或更换电池会非常麻烦。 智能门锁低功耗雷达模块：让门锁更加智能省电节约功耗 在当今信息化时代，智能门锁已经成为人们生活中不可或缺的一部分。对于门锁制造商来说，如何提高门锁的安全性、实用性和便利性，成为他们面对的重要课题。随着人们对门锁智能化的需求越来越高，门锁的能耗问题也成为了门锁制造商需要重视的问题。为此，越来越多的门锁制造商开始推出以低功耗为主题的系列产品。在这样的背景下，智能门锁低功耗雷达模块应运而生。 智能门锁低功耗雷达模块是一种新型技术，其采取雷达技术对门锁周围的物体进行探测，一旦发现门锁附近有人靠近，便会将门锁自动解锁，无需使用钥匙。同时，在保持智能控制的前提下，实现了门锁省电、节约功耗，延长门锁使用寿命。 在使用智能门锁低功耗雷达模块的门锁中，控制电路和自动解锁机制是关键的部件。控制电路采用先进的芯片技术，通过优秀的功耗控制以实现模块化管理。而自动解锁机制不仅可以通过微波信号控制实现门锁的无钥匙解锁，还能够在门锁未处理的情况下自动锁定，保障门锁的安全。 智能门锁低功耗雷达模块的主要特点是：低功耗、高灵敏度和高可靠性。该模块在进行人体检测时，可以远距离探测到距离为5-7米远处的人体信号，目标检测速度极快，而且对门锁周围的环境要求不高。同时，该模块采用了自适应自动补偿技术，能够根据不同环境的变化自动调整信号发射和接收参数，减小误检率。 在使用智能门锁低功耗雷达模块的门锁中，其功耗可以做到非常低，一组电池能够支持门锁持续使用几年左右。而且这样的智能门锁除了具有自动解锁的功能，还可与APP相互匹配，实现了远程操作的便捷性。 总的来说，智能门锁低功耗雷达模块的问世，解决了门锁安全性和省电节省方面的问题，是智能门锁材料不可或缺的一部分。作为门锁制造商，只有不断创新，利用这种新型技术，将会在行业中占据重要的地位。 除了上文所述的主要特点和优势，智能门锁低功耗雷达模块还具有以下几点： 1. 实时监测门锁周围环境变化，通过物体的距离体积和运动来确定是否有人靠近门锁，并控制门锁的开启或关闭，使得门锁更加智能化。 2. 可对门锁附件进行检测，如门挂、门应急照明灯以及紧急呼叫按钮等，并及时给出响应，确保门锁能够正常运作。这样，门锁在不受干扰的情况下，能够 保持安全通道。 3. 通过智能学习技术，能够自适应网站多种环境的变化，让智能门锁低功耗雷达模块更加准确和精细的控制门锁的开关，节约能耗并延长使用寿命。 4. 能够与其他智能电器相连，如智能家居系统、电视等，形成智能家居生态圈，更好地控制家庭访客进出，让生活更加方便。 综上所述，智能门锁低功耗雷达模块的出现，对提升门锁能耗管理和智能化有着重要作用。门锁制造商只有将这些新型技术运用到门锁产品中，才能更加贴合用户需求，满足消费市场的日益增长的智能化需求。
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14
2022-01

微波雷达传感器雷达感应浴室镜上的应用

发布时间： : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用，如今，家用电器的智能化已成为一种常态，越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入，今天就来说说这个话题。 什么是智能浴室镜？智慧型浴室镜，顾名思义，就是卫浴镜子智能化升级，入门级产品基本具备了彩灯和镜面触摸功能，更高档次的产品安装有微波雷达传感器智能感应，当感应到有人接近到一定距离即可开启亮灯或者亮屏操作，也可三色无极调，智能除雾，语音交互，日程安排备忘，甚至在镜子上看电视，听音乐，气象预报，问题查询，智能控制，健康管理等。 智能化雷达感应浴室镜与普通镜的区别，为什么要选TA？，就功能而言，普通浴镜价格用它没有什么压力！而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言，普通浴镜功能单一，而微波雷达传感器智能浴室镜功能创新：镜子灯光色温和亮度可以自由调节，镜面还可以湿手触控，智能除雾，既环保又健康！ 尽管智能浴镜比较新颖，但功能丰富，体验感更好，特别是入门级的智能浴镜，具有基础智能化功能，真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么？ ①确定智能浴室镜的安装位置，因为是安装时在墙壁上打孔，一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时，根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后，在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度，一般智能浴镜的标准安装高度约85cm(从地砖到镜子底)，具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍，可用酒精或30%清洁稀释液擦洗，平时可用干毛巾养护，注意多通风。
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22
2025-05

UWB 芯片：为路由器功能升级注入新活力

发布时间： : 2025-05--22
在当今数字化时代，无线网络技术的发展日新月异。路由器作为家庭和企业网络的核心设备，其性能的提升对于保障高效、稳定的网络连接至关重要。近年来，超宽带（UWB）技术以其独特的优势逐渐崭露头角，并开始在路由器领域得到应用，为路由器的功能拓展和性能优化带来了新的机遇。
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21
2025-05

UWB 技术在电视领域的创新应用与发展趋势

发布时间： : 2025-05--21
在科技飞速发展的当下，电视作为家庭娱乐的核心设备，正不断融入新的技术以提升用户体验。其中，UWB（Ultra-Wideband，超宽带）技术的出现，为电视领域带来了诸多创新应用，从根本上改变了传统电视的交互方式与使用场景。
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20
2025-05

UWB 技术：为游戏设备领域带来革新

发布时间： : 2025-05--20
在科技飞速发展的今天，游戏设备领域也在不断追求创新，以提升玩家的游戏体验。超宽带（UWB）技术作为一项新兴的无线通信技术，正逐渐崭露头角，并在游戏设备领域展现出了巨大的应用潜力。
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