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兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F405RGT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F405RGT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F405xx ARM® Cortex®-M4 32-bit MCU Datasheet Introduction The GD32F405xx device belongs to the connectivity line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F405xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 192 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and two UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS. Additional peripherals as Digital camera interface (DCI) is included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F405xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on. Device information Table 1. GD32F405xx devices features and peripheral list   Part Number GD32F405xx   RE RG RK VG VK VG VK ZG ZK Flash Code Area (KB) 512 512 512 512 512 512 512 512 512   Data Area (KB) 0 512 2560 512 2560 512 2560 512 2560   Total (KB) 512 1024 3072 1024 3072 1024 3072 1024 3072 SRAM (KB) 192 192 192 192 192 192 192 192 192 Timers 16-bit GPTM 8 8 8 8 8 8 8 8 8   32-bit GPTM 2 2 2 2 2 2 2 2 2   Adv. 16-bit TM 2 2 2 2 2 2 2 2 2   Basic TM 2 2 2 2 2 2 2 2 2   SysTick 1 1 1 1 1 1 1 1 1   Watchdog 2 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 1 Connectivity USART+UART 4+2 4+2 4+2 4+2 4+2 4+2 4+2 4+2 4+2   I2C 3 3 3 3 3 3 3 3 3   SPI/I2S 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2   SDIO 1 1 1
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F405RGT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F405xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

Introduction

The GD32F405xx device belongs to the connectivity line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support.
The GD32F405xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 192 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and two UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS. Additional peripherals as Digital camera interface (DCI) is included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications.
The above features make GD32F405xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on.

Device information

Table 1. GD32F405xx devices features and peripheral list

 

Part Number

GD32F405xx

 

RE

RG

RK

VG

VK

VG

VK

ZG

ZK

Flash

Code Area (KB)

512

512

512

512

512

512

512

512

512

 

Data Area (KB)

0

512

2560

512

2560

512

2560

512

2560

 

Total (KB)

512

1024

3072

1024

3072

1024

3072

1024

3072

SRAM (KB)

192

192

192

192

192

192

192

192

192

Timers

16-bit GPTM

8

8

8

8

8

8

8

8

8

 

32-bit GPTM

2

2

2

2

2

2

2

2

2

 

Adv. 16-bit TM

2

2

2

2

2

2

2

2

2

 

Basic TM

2

2

2

2

2

2

2

2

2

 

SysTick

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

Connectivity

USART+UART

4+2

4+2

4+2

4+2

4+2

4+2

4+2

4+2

4+2

 

I2C

3

3

3

3

3

3

3

3

3

 

SPI/I2S

3/2

3/2

3/2

3/2

3/2

3/2

3/2

3/2

3/2

 

SDIO

1

1

1

1

1

1

1

1

1

 

CAN 2.0B

2

2

2

2

2

2

2

2

2

 

USB OTG

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

FS+HS

 

Digital Camera

1

1

1

1

1

1

1

1

1

GPIO

51

51

51

82

82

82

82

114

114

ADC Unit (CHs)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(24)

3(24)

DAC

2

2

2

2

2

2

2

2

2

Package

LQFP64

LQFP100

BGA100

LQFP144

Memory map

Figure 6. GD32F405xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

External Device

 

 

 

AHB

matrix

0xC000 0000 - 0xDFFF FFFF

EXMC - SDRAM

 

 

0xA000 1000 - 0xBFFF FFFF

Reserved

 

 

0xA000 0000 - 0xA000 0FFF

Reserved

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

Reserved

 

 

0x7000 0000 - 0x8FFF FFFF

Reserved

 

 

0x6000 0000 - 0x6FFF FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

AHB2

0x5006 0C00 - 0x5FFF FFFF

Reserved

 

 

0x5006 0800 - 0x5006 0BFF

TRNG

 

 

0x5005 0400 - 0x5006 07FF

Reserved

 

 

0x5005 0000 - 0x5005 03FF

DCI

 

 

0x5004 0000 - 0x5004 FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB1

0x4008 0000 - 0x4FFF FFFF

Reserved

 

 

0x4004 0000 - 0x4007 FFFF

USBHS

 

 

0x4002 BC00 - 0x4003 FFFF

Reserved

 

 

0x4002 B000 - 0x4002 BBFF

Reserved

 

 

0x4002 A000 - 0x4002 AFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

Reserved

 

 

0x4002 6800 - 0x4002 7FFF

Reserved

 

 

0x4002 6400 - 0x4002 67FF

DMA1

 

 

0x4002 6000 - 0x4002 63FF

DMA0

 

 

0x4002 5000 - 0x4002 5FFF

Reserved

 

 

0x4002 4000 - 0x4002 4FFF

BKPSRAM

 

 

0x4002 3C00 - 0x4002 3FFF

FMC

 

 

0x4002 3800 - 0x4002 3BFF

RCU

 

 

0x4002 3400 - 0x4002 37FF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

GPIOI

 

 

0x4002 1C00 - 0x4002 1FFF

GPIOH

 

 

0x4002 1800 - 0x4002 1BFF

GPIOG

 

 

0x4002 1400 - 0x4002 17FF

GPIOF

 

 

0x4002 1000 - 0x4002 13FF

GPIOE

 

 

0x4002 0C00 - 0x4002 0FFF

GPIOD

 

 

0x4002 0800 - 0x4002 0BFF

GPIOC

 

 

0x4002 0400 - 0x4002 07FF

GPIOB

 

 

0x4002 0000 - 0x4002 03FF

GPIOA

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 6C00 - 0x4001 FFFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

Reserved

 

 

0x4001 5800 - 0x4001 67FF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

Reserved

 

 

0x4001 5000 - 0x4001 53FF

Reserved

 

 

0x4001 4C00 - 0x4001 4FFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER10

 

 

0x4001 4400 - 0x4001 47FF

TIMER9

 

 

0x4001 4000 - 0x4001 43FF

TIMER8

 

 

0x4001 3C00 - 0x4001 3FFF

EXTI

 

 

0x4001 3800 - 0x4001 3BFF

SYSCFG

 

 

0x4001 3400 - 0x4001 37FF

Reserved

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

SDIO

 

 

0x4001 2400 - 0x4001 2BFF

Reserved

 

 

0x4001 2000 - 0x4001 23FF

ADC

 

 

0x4001 1800 - 0x4001 1FFF

Reserved

 

 

0x4001 1400 - 0x4001 17FF

USART5

 

 

0x4001 1000 - 0x4001 13FF

USART0

 

 

0x4001 0800 - 0x4001 0FFF

Reserved

 

 

0x4001 0400 - 0x4001 07FF

TIMER7

 

 

0x4001 0000 - 0x4001 03FF

TIMER0

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 C800 - 0x4000 FFFF

Reserved

 

 

0x4000 C400 - 0x4000 C7FF

IVREF

 

 

0x4000 8000 - 0x4000 C3FF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

Reserved

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

CTC

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

I2C2

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 4000 - 0x4000 43FF

I2S2_add

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

I2S1_add

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

 

SRAM

 

 

AHB

matrix

0x2007 0000 - 0x3FFF FFFF

Reserved

 

 

0x2003 0000 - 0x2006 FFFF

Reserved

 

 

0x2002 0000 - 0x2002 FFFF

Reserved

 

 

0x2001 C000 - 0x2001 FFFF

SRAM1(16KB)

 

 

0x2000 0000 - 0x2001 BFFF

SRAM0(112KB)

 

 

 

 

 

 

 

 

Code

 

 

 

 

 

 

 

 

AHB

matrix

0x1FFF C010 - 0x1FFF FFFF

Reserved

 

 

0x1FFF C000 - 0x1FFF C00F

Option bytes(Bank 0)

 

 

0x1FFF 7A10 - 0x1FFF BFFF

Reserved

 

 

0x1FFF 7800 - 0x1FFF 7A0F

OTP(528B)

 

 

0x1FFF 0000 - 0x1FFF 77FF

Boot loader(30KB)

 

 

0x1FFE C010 - 0x1FFE FFFF

Reserved

 

 

0x1FFE C000 - 0x1FFE C00F

Option bytes(Bank 1)

 

 

0x1001 0000 - 0x1FFE BFFF

Reserved

 

 

0x1000 0000 - 0x1000 FFFF

TCMSRAM(64KB)

 

 

0x0830 0000 - 0x0FFF FFFF

Reserved

 

 

0x0800 0000 - 0x082F FFFF

Main Flash(3072KB)

 

 

 

0x0000 0000 - 0x07FF FFFF

Aliased to

the boot device

Pin definitions

Table 2. GD32F405xx pin definitions

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PE2

 

B2

 

1

 

1

 

-

 

I/O

 

5VT

Default: PE2

Alternate: TRACECLK, EVENTOUT

 

PE3

 

A1

 

2

 

2

 

-

 

I/O

 

5VT

Default: PE3

Alternate:TRACED0, EVENTOUT

 

PE4

 

B1

 

3

 

3

 

-

 

I/O

 

5VT

Default: PE4

Alternate:TRACED1, DCI_D4, EVENTOUT

 

PE5

 

C2

 

4

 

4

 

-

 

I/O

 

5VT

Default: PE5

Alternate:TRACED2,TIMER8_CH0, DCI_D6, EVENTOUT

 

PE6

 

D2

 

5

 

5

 

-

 

I/O

 

5VT

Default: PE6

Alternate:TRACED3,TIMER8_CH1, DCI_D7, EVENTOUT

VBAT

E2

6

6

1

P

-

Default: VBAT

PC13- TAMPER-

RTC

 

C1

 

7

 

7

 

2

 

I/O

 

5VT

Default: PC13 Alternate: EVENTOUT

Additional: RTC_TAMP0, RTC_OUT, RTC_TS

 

PC14- OSC32IN

 

D1

 

8

 

8

 

3

 

I/O

 

5VT

Default: PC14

Alternate: EVENTOUT Additional: OSC32IN

 

PC15- OSC32OUT

 

E1

 

9

 

9

 

4

 

I/O

 

5VT

Default: PC15

Alternate: EVENTOUT Additional: OSC32OUT

 

PF0

 

-

 

10

 

-

 

-

 

I/O

 

5VT

Default: PF0

Alternate:I2C1_SDA, EVENTOUT, CTC_SYNC

 

PF1

 

-

 

11

 

-

 

-

 

I/O

 

5VT

Default: PF1

Alternate: I2C1_SCL, EVENTOUT

 

PF2

 

-

 

12

 

-

 

-

 

I/O

 

5VT

Default: PF2

Alternate: I2C1_SMBA, EVENTOUT

 

PF3

 

-

 

13

 

-

 

-

 

I/O

 

5VT

Default: PF3

Alternate: EVENTOUT, I2C1_TXFRAME

Additional: ADC2_IN9

 

PF4

 

-

 

14

 

-

 

-

 

I/O

 

5VT

Default: PF4 Alternate: EVENTOUT

Additional: ADC2_IN14

 

PF5

 

-

 

15

 

-

 

-

 

I/O

 

5VT

Default: PF5 Alternate: EVENTOUT

Additional: ADC2_IN15

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

VSS

F2

16

10

-

P

-

Default: VSS

VDD

G2

17

11

-

P

-

Default: VDD

 

PF6

 

-

 

18

 

-

 

-

 

I/O

 

5VT

Default: PF6 Alternate:TIMER9_CH0, EVENTOUT

Additional: ADC2_IN4

 

PF7

 

-

 

19

 

-

 

-

 

I/O

 

5VT

Default: PF7 Alternate:TIMER10_CH0, EVENTOUT

Additional: ADC2_IN5

 

PF8

 

-

 

20

 

-

 

-

 

I/O

 

5VT

Default: PF8

Alternate: TIMER12_CH0, EVENTOUT Additional: ADC2_IN6

 

PF9

 

-

 

21

 

-

 

-

 

I/O

 

5VT

Default: PF9

Alternate: TIMER13_CH0, EVENTOUT Additional: ADC2_IN7

 

PF10

 

-

 

22

 

-

 

-

 

I/O

 

5VT

Default: PF10

Alternate: DCI_D11, EVENTOUT Additional: ADC2_IN8

 

PH0

 

F1

 

23

 

12

 

5

 

I/O

 

5VT

Default: PH0, OSCIN Alternate: EVENTOUT

Additional: OSCIN

 

PH1

 

G1

 

24

 

13

 

6

 

I/O

 

5VT

Default: PH1, OSCOUT Alternate: EVENTOUT

Additional: OSCOUT

NRST

H2

25

14

7

-

-

Default: NRST

 

PC0

 

H1

 

26

 

15

 

8

 

I/O

 

5VT

Default: PC0

Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10

 

PC1

 

J2

 

27

 

16

 

9

 

I/O

 

5VT

Default: PC1

Alternate:SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT

Additional: ADC012_IN11

 

PC2

 

J3

 

28

 

17

 

10

 

I/O

 

5VT

Default: PC2 Alternate:SPI1_MISO,I2S1_ADD_SD,USBHS_ULPI_DIR, EVENTOUT

Additional: ADC012_IN12

 

PC3

 

K2

 

29

 

18

 

11

 

I/O

 

5VT

Default: PC3 Alternate:SPI1_MOSI,I2S1_SD,USBHS_ULPI_NXT, EVENTOUT

Additional: ADC012_IN13

VDD

-

30

19

-

P

-

Default: VDD

VSSA

J1

31

20

12

P

-

Default: VSSA

VREFN

K1

-

-

-

P

-

Default: VREF-

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

VREFP

L1

32

21

-

P

-

Default: VREF+

VDDA

M1

33

22

13

P

-

Default: VDDA

 

 

PA0-WKUP

 

 

L2

 

 

34

 

 

23

 

 

14

 

 

I/O

 

 

5VT

Default: PA0 Alternate:TIMER1_CH0,TIMER1_ETI,TIMER4_CH0, TIMER7_ETI,USART1_CTS, UART3_TX, EVENTOUT

Additional: ADC012_IN0, WKUP

 

 

PA1

 

 

M2

 

 

35

 

 

24

 

 

15

 

 

I/O

 

 

5VT

Default: PA1

Alternate:TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT

Additional: ADC012_IN1

 

 

PA2

 

 

K3

 

 

36

 

 

25

 

 

16

 

 

I/O

 

 

5VT

Default: PA2 Alternate:TIMER1_CH2,TIMER4_CH2,TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT

Additional: ADC012_IN2

 

 

PA3

 

 

L3

 

 

37

 

 

26

 

 

17

 

 

I/O

 

 

5VT

Default: PA3 Alternate:TIMER1_CH3,TIMER4_CH3,TIMER8_CH1, I2S1_MCK,USART1_RX,USBHS_ULPI_D0, EVENTOUT

Additional: ADC012_IN3

VSS

-

38

27

18

P

-

Default: VSS

NC

E3

-

-

-

-

-

-

VDD

-

39

28

19

P

-

Default: VDD

 

 

PA4

 

 

M3

 

 

40

 

 

29

 

 

20

 

 

I/O

 

 

TTa

Default: PA4

Alternate:SPI0_NSS,SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, EVENTOUT

Additional: ADC01_IN4, DAC_OUT0

 

 

PA5

 

 

K4

 

 

41

 

 

30

 

 

21

 

 

I/O

 

 

TTa

Default: PA5

Alternate:TIMER1_CH0,TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT

Additional: ADC01_IN5, DAC_OUT1

 

 

PA6

 

 

L4

 

 

42

 

 

31

 

 

22

 

 

I/O

 

 

5VT

Default: PA6 Alternate:TIMER0_BRKIN,TIMER2_CH0,TIMER7_BRKIN,SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT

Additional: ADC01_IN6

 

 

PA7

 

 

M4

 

 

43

 

 

32

 

 

23

 

 

I/O

 

 

5VT

Default: PA7 Alternate:TIMER0_CH0_ON,TIMER2_CH1,

TIMER7_CH0_ON,SPI0_MOSI,TIMER13_CH0, EVENTOUT

Additional: ADC01_IN7

 

PC4

 

K5

 

44

 

33

 

24

 

I/O

 

5VT

Default: PC4

Alternate: EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

 

 

 

 

 

 

Additional: ADC01_IN14

 

PC5

 

L5

 

45

 

34

 

25

 

I/O

 

5VT

Default: PC5

Alternate:USART2_RX, EVENTOUT Additional: ADC01_IN15

 

 

PB0

 

 

M5

 

 

46

 

 

35

 

 

26

 

 

I/O

 

 

5VT

Default: PB0 Alternate:TIMER0_CH1_ON,TIMER2_CH2,TIMER7_CH1_ON,SPI2_MO SI,I2S2_SD,USBHS_ULPI_D1, SDIO_D1, EVENTOUT

Additional: ADC01_IN8, IREF

 

 

PB1

 

 

M6

 

 

47

 

 

36

 

 

27

 

 

I/O

 

 

5VT

Default: PB1 Alternate:TIMER0_CH2_ON,TIMER2_CH3,TIMER7_CH2_ON,USBHS_ ULPI_D2, SDIO_D2, EVENTOUT

Additional: ADC01_IN9

 

PB2

 

L6

 

48

 

37

 

28

 

I/O

 

5VT

Default: PB2, BOOT1 Alternate:TIMER1_CH3,SPI2_MOSI,I2S2_SD,USBHS_ULPI_D4,

SDIO_CK, EVENTOUT

 

PF11

 

-

 

49

 

-

 

-

 

I/O

 

5VT

Default: PF11

Alternate: DCI_D12, EVENTOUT

 

PF12

 

-

 

50

 

-

 

-

 

I/O

 

5VT

Default: PF12

Alternate: EVENTOUT

VSS

-

51

-

-

P

-

Default: VSS

VDD

-

52

-

-

P

-

Default: VDD

 

PF13

 

-

 

53

 

-

 

-

 

I/O

 

5VT

Default: PF13

Alternate: EVENTOUT

 

PF14

 

-

 

54

 

-

 

-

 

I/O

 

5VT

Default: PF14

Alternate: EVENTOUT

 

PF15

 

-

 

55

 

-

 

-

 

I/O

 

5VT

Default: PF15

Alternate: EVENTOUT

 

PG0

 

-

 

56

 

-

 

-

 

I/O

 

5VT

Default: PG0

Alternate: EVENTOUT

 

PG1

 

-

 

57

 

-

 

-

 

I/O

 

5VT

Default: PG1

Alternate: EVENTOUT

 

PE7

 

M7

 

58

 

38

 

-

 

I/O

 

5VT

Default: PE7

Alternate: TIMER0_ETI, EVENTOUT

 

PE8

 

L7

 

59

 

39

 

-

 

I/O

 

5VT

Default: PE8

Alternate: TIMER0_CH0_ON, EVENTOUT

 

PE9

 

M8

 

60

 

40

 

-

 

I/O

 

5VT

Default: PE9

Alternate: TIMER0_CH0, EVENTOUT

VSS

-

61

-

-

P

-

Default: VSS

VDD

-

62

-

-

P

-

Default: VDD

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PE10

 

L8

 

63

 

41

 

-

 

I/O

 

5VT

Default: PE10

Alternate: TIMER0_CH1_ON, EVENTOUT

 

PE11

 

M9

 

64

 

42

 

-

 

I/O

 

5VT

Default: PE11

Alternate:TIMER0_CH1, EVENTOUT

 

PE12

 

L9

 

65

 

43

 

-

 

I/O

 

5VT

Default: PE12

Alternate:TIMER0_CH2_ON, EVENTOUT

 

PE13

 

M10

 

66

 

44

 

-

 

I/O

 

5VT

Default: PE13

Alternate:TIMER0_CH2, EVENTOUT

 

PE14

 

M11

 

67

 

45

 

-

 

I/O

 

5VT

Default: PE14

Alternate:TIMER0_CH3, EVENTOUT

 

PE15

 

M12

 

68

 

46

 

-

 

I/O

 

5VT

Default: PE15

Alternate: TIMER0_BRKIN, EVENTOUT

 

PB10

 

L10

 

69

 

47

 

29

 

I/O

 

5VT

Default: PB10

Alternate:TIMER1_CH2,I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK,USART2_TX,USBHS_ULPI_D3, SDIO_D7, EVENTOUT

 

PB11

 

K9

 

70

 

48

 

30

 

I/O

 

5VT

Default: PB11

Alternate:TIMER1_CH3,I2C1_SDA,I2S_CKIN,USART2_RX,USBHS_UL PI_D4, EVENTOUT

NC

L11

71

49

31

P

-

Default: VCORE

VSS

F12

-

-

-

P

-

Default: VSS

VDD

G12

72

50

32

P

-

Default: VDD

 

PB12

 

L12

 

73

 

51

 

33

 

I/O

 

5VT

Default: PB12 Alternate:TIMER0_BRKIN,I2C1_SMBA,SPI1_NSS, I2S1_WS,

USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT

 

 

 

PB13

 

 

 

K12

 

 

 

74

 

 

 

52

 

 

 

34

 

 

 

I/O

 

 

 

5VT

Default: PB13 Alternate:TIMER0_CH0_ON,SPI1_SCK,I2S1_CK, USART2_CTS,CAN1_TX,USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME

Additional: USBHS_VBUS

 

PB14

 

K11

 

75

 

53

 

35

 

I/O

 

5VT

Default: PB14 Alternate:TIMER0_CH1_ON,TIMER7_CH1_ON,SPI1_MISO,I2S1_ADD_

SD,USART2_RTS,TIMER11_CH0,USBHS_DM, EVENTOUT

 

PB15

 

K10

 

76

 

54

 

36

 

I/O

 

5VT

Default: PB15 Alternate:RTC_REFIN,TIMER0_CH2_ON,TIMER7_CH2_ON,

SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT

 

PD8

 

-

 

77

 

55

 

-

 

I/O

 

5VT

Default: PD8

Alternate: USART2_TX, EVENTOUT

 

PD9

 

K8

 

78

 

56

 

-

 

I/O

 

5VT

Default: PD9

Alternate: USART2_RX, EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PD10

 

J12

 

79

 

57

 

-

 

I/O

 

5VT

Default: PD10

Alternate: USART2_CK, EVENTOUT

 

PD11

 

J11

 

80

 

58

 

-

 

I/O

 

5VT

Default: PD11

Alternate: USART2_CTS, EVENTOUT

 

PD12

 

J10

 

81

 

59

 

-

 

I/O

 

5VT

Default: PD12

Alternate:TIMER3_CH0,USART2_RTS , EVENTOUT

 

PD13

 

H12

 

82

 

60

 

-

 

I/O

 

5VT

Default: PD13

Alternate: TIMER3_CH1, EVENTOUT

VSS

-

83

-

-

P

-

Default: VSS

VDD

-

84

-

-

P

-

Default: VDD

 

PD14

 

H11

 

85

 

61

 

-

 

I/O

 

5VT

Default: PD14

Alternate: TIMER3_CH2, EVENTOUT

 

PD15

 

H10

 

86

 

62

 

-

 

I/O

 

5VT

Default: PD15

Alternate:TIMER3_CH3, EVENTOUT, CTC_SYNC

 

PG2

 

-

 

87

 

-

 

-

 

I/O

 

5VT

Default: PG2

Alternate: EVENTOUT

 

PG3

 

-

 

88

 

-

 

-

 

I/O

 

5VT

Default: PG3

Alternate: EVENTOUT

 

PG4

 

-

 

89

 

-

 

-

 

I/O

 

5VT

Default: PG4

Alternate: EVENTOUT

 

PG5

 

-

 

90

 

-

 

-

 

I/O

 

5VT

Default: PG5

Alternate: EVENTOUT

 

PG6

 

-

 

91

 

-

 

-

 

I/O

 

5VT

Default: PG6

Alternate: DCI_D12, EVENTOUT

 

PG7

 

-

 

92

 

-

 

-

 

I/O

 

5VT

Default: PG7

Alternate:USART5_CK, DCI_D13, EVENTOUT

 

PG8

 

-

 

93

 

-

 

-

 

I/O

 

5VT

Default: PG8

Alternate:USART5_RTS, EVENTOUT

VSS

-

94

-

-

P

-

Default: VSS

VDD

-

95

-

-

P

-

Default: VDD

 

PC6

 

E12

 

96

 

63

 

37

 

I/O

 

5VT

Default: PC6 Alternate:TIMER2_CH0,TIMER7_CH0,I2S1_MCK,USART5_TX,

SDIO_D6, DCI_D0, EVENTOUT

 

PC7

 

E11

 

97

 

64

 

38

 

I/O

 

5VT

Default: PC7

Alternate:TIMER2_CH1,TIMER7_CH1,SPI1_SCK,I2S1_CK,I2S2_MCK, USART5_RX,SDIO_D7,DCI_D1,EVENTOUT

 

PC8

 

E10

 

98

 

65

 

39

 

I/O

 

5VT

Default: PC8

Alternate:TRACED0,TIMER2_CH2,TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

PC9

 

D12

 

99

 

66

 

40

 

I/O

 

5VT

Default: PC9 Alternate:CK_OUT1,TIMER2_CH3,TIMER7_CH3,I2C2_SDA, I2S_CKIN,

SDIO_D1, DCI_D3, EVENTOUT

 

PA8

 

D11

 

100

 

67

 

41

 

I/O

 

5VT

Default: PA8 Alternate:CK_OUT0,TIMER0_CH0,I2C2_SCL,USART0_CK,

USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC

 

 

PA9

 

 

D10

 

 

101

 

 

68

 

 

42

 

 

I/O

 

 

5VT

Default: PA9 Alternate:TIMER0_CH1,I2C2_SMBA,SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT

Additional: USBFS_VBUS

 

PA10

 

C12

 

102

 

69

 

43

 

I/O

 

5VT

Default: PA10 Alternate:TIMER0_CH2,USART0_RX,USBFS_ID,DCI_D1, EVENTOUT,

I2C2_TXFRAME

 

PA11

 

B12

 

103

 

70

 

44

 

I/O

 

5VT

Default: PA11 Alternate:TIMER0_CH3,USART0_CTS,USART5_TX,CAN0_RX,

USBFS_DM, EVENTOUT

 

PA12

 

A12

 

104

 

71

 

45

 

I/O

 

5VT

Default: PA12 Alternate:TIMER0_ETI,USART0_RTS,USART5_RX, CAN0_TX,

USBFS_DP, EVENTOUT

 

PA13

 

A11

 

105

 

72

 

46

 

I/O

 

5VT

Default: JTMS, SWDIO, PA13

Alternate: EVENTOUT

NC

C11

106

73

47

-

-

-

VSS

F11

107

74

-

P

-

Default: VSS

VDD

G11

108

75

48

P

-

Default: VDD

 

PA14

 

A10

 

109

 

76

 

49

 

I/O

 

5VT

Default: JTCK, SWCLK, PA14

Alternate: EVENTOUT

 

PA15

 

A9

 

110

 

77

 

50

 

I/O

 

5VT

Default: JTDI, PA15

Alternate:TIMER1_CH0,TIMER1_ETI,SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT

 

PC10

 

B11

 

111

 

78

 

51

 

I/O

 

5VT

Default: PC10

Alternate:SPI2_SCK,I2S2_CK,USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT

 

PC11

 

C10

 

112

 

79

 

52

 

I/O

 

5VT

Default: PC11 Alternate:I2S2_ADD_SD,SPI2_MISO,USART2_RX, UART3_RX,

SDIO_D3, DCI_D4, EVENTOUT

 

PC12

 

B10

 

113

 

80

 

53

 

I/O

 

5VT

Default: PC12 Alternate:I2C1_SDA,SPI2_MOSI,I2S2_SD,USART2_CK, UART4_TX,

SDIO_CK, DCI_D9, EVENTOUT

PD0

C9

114

81

-

I/O

5VT

Default: PD0

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

 

 

 

 

 

 

Alternate:SPI2_MOSI, I2S2_SD, CAN0_RX, EVENTOUT

 

PD1

 

B9

 

115

 

82

 

-

 

I/O

 

5VT

Default: PD1

Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EVENTOUT

 

PD2

 

C8

 

116

 

83

 

54

 

I/O

 

5VT

Default: PD2

Alternate:TIMER2_ETI,UART4_RX,SDIO_CMD,DCI_D11, EVENTOUT

 

PD3

 

B8

 

117

 

84

 

-

 

I/O

 

5VT

Default: PD3

Alternate:TRACED1,SPI1_SCK,I2S1_CK, USART1_CTS, DCI_D5,EVENTOUT

 

PD4

 

B7

 

118

 

85

 

-

 

I/O

 

5VT

Default: PD4

Alternate: USART1_RTS, EVENTOUT

 

PD5

 

A6

 

119

 

86

 

-

 

I/O

 

5VT

Default: PD5

Alternate: USART1_TX, EVENTOUT

VSS

-

120

-

-

P

-

Default: VSS

VDD

-

121

-

-

P

-

Default: VDD

 

PD6

 

B6

 

122

 

87

 

-

 

I/O

 

5VT

Default: PD6

Alternate:SPI2_MOSI,I2S2_SD,USART1_RX, DCI_D10, EVENTOUT

 

PD7

 

A5

 

123

 

88

 

-

 

I/O

 

5VT

Default: PD7

Alternate:USART1_CK, EVENTOUT

 

PG9

 

-

 

124

 

-

 

-

 

I/O

 

5VT

Default: PG9

Alternate:USART5_RX, DCI_VSYNC, EVENTOUT

 

PG10

 

-

 

125

 

-

 

-

 

I/O

 

5VT

Default: PG10

Alternate: DCI_D2,EVENTOUT

 

PG11

 

-

 

126

 

-

 

-

 

I/O

 

5VT

Default: PG11

Alternate: DCI_D3, EVENTOUT

 

PG12

 

-

 

127

 

-

 

-

 

I/O

 

5VT

Default: PG12

Alternate: USART5_RTS, EVENTOUT

 

PG13

 

-

 

128

 

-

 

-

 

I/O

 

5VT

Default: PG13

Alternate:TRACED2, USART5_CTS, EVENTOUT

 

PG14

 

-

 

129

 

-

 

-

 

I/O

 

5VT

Default: PG14

Alternate:TRACED3, USART5_TX, EVENTOUT

VSS

-

130

-

-

P

-

Default: VSS

VDD

-

131

-

-

P

-

Default: VDD

 

PG15

 

-

 

132

 

-

 

-

 

I/O

 

5VT

Default: PG15

Alternate:USART5_CTS,DCI_D13, EVENTOUT

 

PB3

 

A8

 

133

 

89

 

55

 

I/O

 

5VT

Default: JTDO, PB3 Alternate:TRACESWO,TIMER1_CH1,SPI0_SCK,SPI2_SCK, I2S2_CK,

USART0_RX, I2C1_SDA, EVENTOUT

 

PB4

 

A7

 

134

 

90

 

56

 

I/O

 

5VT

Default: NJTRST, PB4

Alternate:TIMER2_CH0,SPI0_MISO,SPI2_MISO,

 

 

 

Pin Name

Pins

Pin Type(1)

I/O(2) Level

 

 

Functions description

 

BGA100

LQFP144

LQFP100

LQFP64

 

 

 

 

 

 

 

 

 

 

I2S2_ADD_SD,I2C2_SDA,SDIO_D0,EVENTOUT, I2C0_TXFRAME

 

PB5

 

C5

 

135

 

91

 

57

 

I/O

 

5VT

Default: PB5

Alternate:TIMER2_CH1,I2C0_SMBA,SPI0_MOSI,SPI2_MOSI,I2S2_SD, CAN1_RX,USBHS_ULPI_D7,ETH_PPS_OUT, DCI_D10, EVENTOUT

 

PB6

 

B5

 

136

 

92

 

58

 

I/O

 

5VT

Default: PB6 Alternate:TIMER3_CH0,I2C0_SCL,USART0_TX,CAN1_TX, DCI_D5,

EVENTOUT

 

PB7

 

B4

 

137

 

93

 

59

 

I/O

 

5VT

Default: PB7

Alternate:TIMER3_CH1,I2C0_SDA,USART0_RX, DCI_VSYNC, EVENTOUT

BOOT0

A4

138

94

60

I/O

5VT

Default: BOOT0

 

PB8

 

A3

 

139

 

95

 

61

 

I/O

 

5VT

Default: PB8

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT

 

PB9

 

B3

 

140

 

96

 

62

 

I/O

 

5VT

Default: PB9

Alternate:TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT

 

PE0

 

C3

 

141

 

97

 

-

 

I/O

 

5VT

Default: PE0

Alternate:TIMER3_ETI, DCI_D2, EVENTOUT

 

PE1

 

A2

 

142

 

98

 

-

 

I/O

 

5VT

Default: PE1

Alternate:TIMER0_CH1_ON, DCI_D3, EVENTOUT

VSS

D3

-

99

63

P

-

Default: VSS

PDR_ON

H3

143

-

-

P

-

Default: PDR_ON

VDD

C4

144

100

64

P

-

Default: VDD

Notes:
1.Type: I = input, O = output, P = power.
2.I/O Level: 5VT = 5 V tolerant.

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 168 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 3072 Kbytes of Flash memory, including code Flash and data Flash
512B of OTP (one-time programmable) memory
192 KB of SRAM

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and

accessed (R/W) at CPU clock speed with zero wait states. Up to 192 Kbytes of inner SRAM is composed of SRAM0 (112KB) and SRAM1 (16KB) that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex®-M4 core. The additional 4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the VDD power supply is down. The Figure of GD32F405xx memory map shows the memory map of the GD32F405xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 168 MHz. The maximum frequency of the two APB domains including APB1 is 42 MHz and APB2 is 84 MHz. See Figure 6 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal 30KB of information blocks for the boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART2, and USB Device FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes.

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.6MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for external battery power supply (VBAT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

Two 12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for DMA1)
Support independent 8, 16, 32-bit memory and peripheral transfer
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO and DCI

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 114 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable

There are up to 140 general purpose I/O pins (GPIO) in GD32F405xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced-control timer (TM0 & TM7), eight 16-bit general-purpose timers (TM2, TM3, TM8 ~ TM13), two 32-bit general-purpose timers (TM1 & TM4) and two 16- bit basic timer (TM5 & TM6)
Up to 4 independent channels of PWM, output compare or input capture for each general- purpose timer (GPTM) and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog and window watchdog)

The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 & TM4 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM2 & TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM9 ~ TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F405xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 32 kHz internal RC and as it operates independently of the main clock, it can operate in deep sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC) and backup registers

Independent binary-coded decimal (BCD) format timer/counter with twenty 32-bit backup registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

Inter-integrated circuit (I2C)

Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz (Fast mode)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Up to four USARTs and two UARTs with operating frequency up to 9 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4) are used
to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1 and SPI2
Support either master or slave mode Audio
Sampling frequencies from 8 kHz up to 192 kHz are supported.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32F405xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequencies from 8 kHz to 192 kHz is supported.

Universal serial bus on-the-go full-speed (USB OTG FS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator support crystal-less operation
Internal main PLL for USB CLK compliantly
Internal USB OTG FS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation.

Universal serial bus on-the-go high-speed (USB OTG HS)

One USB device/host/OTG high-speed Interface with frequency up to 480 Mbit/s
An external PHY device connected to the ULPI is required when using in HS mode

USB OTG HS supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller provides ULPI interface for external USB PHY integration and it also contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB
2.0 protocol. HUB connection is supported when USB HS operates at high-speed in host mode. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USB HS and system.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Secure digital input and output card interface (SDIO)

Support SD2.0/SDIO2.0/MMC4.2 host interface

The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.

Digital camera interface (DCI)

Digital video/picture capture
8/10/12/14 data width supported
High transfer efficiency with DMA interface
Video/picture crop supported
Various pixel formats supported including JPEG/YCrCb/RGB
Hard/embedded synchronous signals supported

DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

BGA100 (GDF405VxH), LQFP144 (GD32F405Zx), LQFP100 (GD32F405Vx) and LQFP64 (GD32F405Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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雷达传感器摄像头视频复合障碍物检测识别防撞探测系统

雷达传感器摄像头视频复合障碍物检测识别防撞探测系统,普通公共交通工具有地铁、公交、轻轨等,由于其不排放SO2等有毒尾气等有害气体的优点,在国内许多城市交通建设部门受到青睐。为保证行车安全,电车一般都是在马路中间行驶,在人行横道与拐弯处有必要采取保护措施。作为一种比较成熟的产品,毫米波雷达的检测性能十分稳定,对环境要求不高,即使在雨雪天气下,它也能很好地工作。其功能主要是对目标距离的测量,对目标的速度和方位进行测量。除功能多样外,毫米波雷达在其它方面也有其优势。比如,它的结构很简单,利用新的RF收发芯片,很快就能形成一套完整的系统;由于工作频率的关系,毫米波雷达发射功率很小,并且可以达到很高的分辨率和灵敏度;与此同时,它的天线可以做的非常小,在主动防撞系统中,毫米波雷达传感器已经成为必然的选择。经实践检验,雷达系统存在人和车不能检测的问题,因此该系统增加了视频设备对近距离行人、单车和车辆的探测预警。 电车雷达视频复合防撞系统是利用雷达传感器和视频传感器联合检测列车行驶前障碍物,评估其危害程度,给出相应的等级预警信号。它具有检测有轨车前障碍物、危险预警和实现与车信号系统控制主机网络通讯等功能。它主要由雷达传感器、雷达系统主机、视频传感器、视频系统主机、防撞障碍物视频融合系统组成。障碍防撞系统主要包括雷达系统和视频系统,它是对远距离车辆目标的跟踪预警,以及视频系统对近距离目标的探测预警。 雷达系统构成障碍物防撞雷达系统由雷达传感器、数据处理模块、电源模块、线缆、安装架和系统软件组成,其中数据处理模块和电源模块采用一体化设计构成系统主机。视频系统构成视频系统,由视频传感器、摄像单元、数据转换和供电模块组成,其中包含镜头和视频处理模块,摄象机对视频数据进行采集和处理,数据转换和供电模块负责视频系统的供电,以及视频系统和雷达主机之间的数据传输功能。 采用毫米波雷达传感器FMCW体制实现了对障碍物的探测与识别,通过两次多收天线方式,可有效地检测多个目标参数。雷达法是利用障碍物反射电磁波现象来发现和确定目标位置的。该方案将障碍物探测雷达安装在有轨电车上,工作于24GHz毫米波段,采用FM连续波测量障碍物距离,并采用数字波束形成技术进行目标定位。接受波束形成器利用n个接收天线阵元构成的天线阵列,接收波束形成技术将多个接收天线所接收的信号合成一个波束。综合的信号在接收波束增强时,通过相位补偿确定波束方向,并根据所需接收回波信号,通过相位补偿确定波束角,可以接收到所需的回波信号。所以起到了空间滤波作用。该接收天线具有较高的灵敏度,能够检测到每一个接收波束在空间辐射范围内具有与多个接收波束相同的微弱信号,因此从技术实现上来说,与多波束收发相比,多波束接收更容易实现,且易于处理,故采用宽波束、多波束接收方式。该雷达安装在有轨电车上,其天线采用两次多接收方式,可进行短距离和远距离混合测量。近距离测量采用宽波束,雷达的方位角50°,垂直波束角4°,探测距离60m;远距离测量采用窄波束,雷达的方位角20°,垂直波束角4°,探测距离200m。窄波束主要用于捕捉远距离目标,帮助驾驶员及时发现目标,并有足够的反应时间,可以有效地避免有轨电车在通过交叉路口时,由于某些突发事件而造成的交通事故。宽频雷达波束主要捕获车头近区域内视觉盲区不易察觉的近距目标,从而避免有轨电车发生一系列因盲区而引起的碰撞事故。 通过距离-多普勒二维回波处理,实现目标距离、速度信息的一体化测量,改进数据处理的实时性,提高信号处理累积增益,从而有效地提高雷达传感器系统对目标的检测灵敏度,是解决多目标识别问题的一种有效方法。多普勒处理方法利用锯齿形调频连续波信号,通过采集多个循环的数据获取平均值,并以每个周期的实际值减去该平均值,可有效地抑制固定杂波的部分,从而简化了后续信号处理。在复杂环境下,该算法还可实现运动目标的距离和速度的去耦合。雷达波形采用锯齿波线性调频连续波,该雷达信号由单扫频信号构成,每一周期仅有一个调频斜率,即信号频率在一个周期内先逐渐升高,到设定值后迅速降至初始值,循环重复。这类信号对于现有的信号发生器来说是比较容易产生的,因此在现代雷达系统中得到了更广泛的应用。 视频近距探测系统雷达传感器视频复合防撞系统视频系统采用成熟的产品。它主要应用于对近距离目标的前方避碰预警(FCW)和行人碰撞预警(PCW)。录像机的摄像是非广角拍摄,拍摄角度有限,因此需要将摄像机安装在距离中轴线左右两侧15cm以内,同时安装位置应尽量不遮挡司机视线。在雷达视频复合防撞系统中,由视频采集器的主机过滤,然后与雷达发出的报警信息融合,输出预警信息,对有轨电车驾驶员发出警告信息,避免碰撞。 雷达传感器限界内障碍物检测识别障碍物探测系统能在有轨电车运行限界内探测到目标、距离、速度、利用现代数字滤波器,根据其运动特性(近/远)的运动特性,对目标轨迹进行测向计算,再利用现代数字滤波器预测它的运动轨迹。计算评价有轨电车目标移动速度和制动特性时,对电车危险程度进行评定。静态指标。在限界内要识别静态目标,并移除有轨。动态目标。在限界内,动态目标应该按照其运动轨迹进行危险度评价。障碍检测系统不能误报、漏报前方障碍。 雷达传感器限界外障碍物检测识别障碍物探测系统,能在有轨电车在运行过程中探测到目标,测速、测速、方位,然后用现代数字滤波跟踪预测有轨电车的轨迹。通过运动特征(接近/远离等)、到电车的距离、目标物的速度、电车的速度、制动特性,计算出其对电车的危险程度。静态指标。在限制范围外,应该去掉静态目标。动态目标。在限定范围外,需要确定动态目标,并根据其运动轨迹判断是否有害。 坡道、弯道障碍物检测识别障碍物检测系统根据线路数据和列车定位信息,识别出当前的列车坡道、弯道路况等线路状态。 (1)斜坡。对于上、下坡道道路,障碍物检测系统需要分析线路坡度等情况,并进行障碍物报警识别,不能因为上、下坡道的误报或漏报。 (2)弯曲。障碍物检测系统在弯道路况下,对弯道转弯半径等线路状况进行分析,调整线路限界,并进行障碍物报警识别,避免误报和误报。 平交路口障碍物检测识别障碍检测系统根据线路数据和列车定位信息,判断列车当前位置是否是平交口。对于交叉路口的路况,障碍物检测系统需要考虑前方车辆较多和车头近距盲区的情况,调整探测分析和预警算法,对障碍物进行报警识别,不应因平交路口造成误报或漏报。 多级预警功能障碍探测系统可以检测32个障碍物的距离、方位及移动障碍物的轨迹。该系统的处理中心根据检测信息和电车本身的运动参数,例如列车运行速度等,来确定碰撞可能发生碰撞的位置和预计碰撞的时间,识别前方障碍物的危险等级,并将危险目标实时传送到车载设备上。依据电车紧急制动速率,常用制动速率将预警情况分为三种,分别为有碰撞危险、有无可避免碰撞的可能性。如果障碍物检测系统检测到障碍物有碰撞危险,就会发出警报。火车在靠近障碍物位置或可能发生碰撞的地点时,系统判定列车极有可能发生碰撞,应及时采取常规的制动措施。并且当列车接近于障碍物位置或可能发生碰撞的地点时,系统判定为无法避免的碰撞,必须采取紧急制动措施。 视频系统功能(1)正面防撞。发出警告音的声音是在与前车有可能发生碰撞之前的2.7秒内;警报声是一连串的高声蜂鸣声。(2)低转速防撞。警告音可能是在与前车低速相撞之前发出警告声;在30km/h以下的时速,以一系列短促的高音量蜂鸣声报警。(3)行人躲避碰撞。在经过车辆前行的道路时,行人发出警报;只有当日间车速低于50km/h时才启动;在昏暗或夜间,系统不能工作;报警声是一连串高音蜂鸣声。气候、光照等因素会对视频系统的识别和反应能力产生很大影响,如部分或完全阻隔视觉传感器的视野,将导致视频系统功能的丧失或减弱。 障碍防撞雷达视频组合系统为有轨电车运行提供辅助安全预警功能,提示可能出现的危险;雷达传感器和录像设备虽然已应用到相关领域的先进创新技术,但是仍然无法保证百分之一百的准确探测车辆和行人,因此无法保证提供所有相应的声音警告。由于道路、道路设施、天气等因素都会对系统识别和反应能力产生很大影响,因此,应继续遵循安全驾驶规范和安全驾驶惯例,并辅以该系统的使用。
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03
2021-12

以gd芯片代理商GD32为基础制造业实现智能化通用变频方案GD集成栅极驱动器赋能电动工具应用

发布时间: : 2021-12--03
以gd芯片代理商GD32为基础制造业实现智能化通用变频方案GD集成栅极驱动器赋能电动工具应用,以GD32F303为基础,支持制造业实现智能化改造,通用变频方案设计。2020年9月,我国确定了碳达峰和2060年碳中和的目标,今后40年内实现碳减排净零排放对中国来说将是一项艰巨的任务。对电动机行业而言,电机在工业领域占据着重要地位,据统计,我国电机年消耗电力总量的69%和工业用电总量的75%左右。所以降低电机寿命中的碳排放,加快电机减碳过程是电机工业面临的重要课题。变频器技术能够正确地控制交流电动机的转速,使其处于节能状态,是对传统电动机系统进行调速,提高电动机系统运行效率的关键措施。常规变频器具有体积大、性能低、价格高等特点,另外对环境也有一定要求,对于分散控制的场合,传统变频器很难满足工业应用的需要。 本文以以gd芯片代理商GD32MCU为核心的VF/矢量变频器控制系统,采用模块化设计,控制面板,用户界面可根据需要自由组合,安装方便.编程及初始化设计,容易实现异步电机调速要求。结合总线技术,可以方便地与控制系统.集散系统相连,实现计算机驱动系统控制和工厂车间集中控制。所以本变频器在汽车、食品、物料输送.工业控制等智能制造领域有着广阔的应用空间。 方案特点: 设计内核采用GD32F303RCT6控制,使系统结构简单、易于实现、成本低、可靠性高。系统在优化硬件结构的同时,不降低系统性能,硬件系统模块清晰、直观,便于安装使用和程序初始化。采用SVPWM控制技术,可以有效地降低逆变器输出电压谐波成份,提高电压利用率,提高控制精度。 以gd芯片代理商GD32F303介绍: 1、Cortex®-M4内核@120MHz。 2、软件和硬件支持DSP指令。 3、flash存取为0等待。 4、内建256KB到3072KB的闪存。 5、内装48KB到96KBSRAM。 6、EXMC接口支持外部SDRAM。 7、多达5个UART(9Mbit/s) 8、多达3个SPI(30Mbit/s) 9、多达2个I2C(400Kbit/s) 10、多可达到2CAN2.0B。 11、I2S的高值是2。 12、SDIO.EthernetMAC支持。 13、USBOTGFS支持。 14、高达3个12位,2.6MSPSADC(多达24路) 15、多达为2DAC。 16、备用电流是2毫安。 关键的控制原则与实施: 该调制器具有线性范围宽、高次谐少、易实现数字化等特点,广泛应用于异步电动机。MOS管在传统的三相桥驱动电路中有8种开关组合,即000.001.010.011.100.101.110.111。000.111是零向量。6个非零基压空间矢量把αβ平面分成6个扇区。通过对8个基本空间电压矢量作用时间的控制,得出了各基本空间电压矢量作用时间及输出次序,获得圆周旋转磁场。 TIMER0模块是以gd芯片代理商GD32中的一个增强型定时器模块,天生用于电机控制,可产生3组6路PWM,每组2路PWM可作为互补,并可带死区使用,可用于驱动H桥。用三通道TIM0模块产生总共6路PWM输出。以下是详细的步骤: 打开TIM0时钟,将相应的IO口设置为多路输出。 将TIM0设定为ARR和PSC,当TIM0打开时钟后,设定ARR和PSC两个寄存器的值,以控制输出PWM的周期。 为TIM0_CH0.TIM0_CH1.TIM0_CH2设置PWM模式。 通过TIM0的CH0~CH2输出,使能量达到TIM0。 修正TIM0_CCR1~TIM0_CCR2以控制占空比。 利用上述配置,配合GD32F303运算能力,实时调整占空比,达到矢量控制效果。 赋能型电动工具应用GD30DR8306高集成栅极驱动器,电气工具是以电为动力的各种通用构造器具,一般还是依靠工人手工操作,广泛用于建筑装修、轻工制造等领域。与纯人工手工工具相比,电动工具通过电力大幅度提高工具的扭力.转速.冲击力等,大大提高工作效率。普通电动工具有电钻.电动砂轮机.电动扳手.电动螺丝刀.电锤.电钻.混凝土振动器.电刨等。根据等级,电动工具可以分为专业级、工用级和通用级。 1、根据市场规模,2020年全球电动工具市场约为360亿美元,2025年约为460亿美元,而2017年CAGR约为5.3%。 2、从市场细分来看,专业级以上电动工具占商业用途的比重为63.2%,相对于一般居民用途的30.8%,这种结构在较长时期内将保持基本稳定。 3、从区域市场上看,2019年北美市场份额.亚太市场份额与欧洲份额持平,分别为30.8%.28.7%和28.6,另外11.9%的地区,如拉美非洲,这类结构同样也将保持相对稳定,到2025年,亚太地区将略升至31.1%。 以gd芯片代理商GD30DR8306驱动器主要特性: GD30DR8306是三相栅极驱动器,带有可选的DC/DC降压控制器。所述芯片包含三个半桥驱动器,每个驱动器可以驱动两个NMOSFET,并支持大的拉电流和1A的灌流能力。根据应用中所用功率MOSFET的不同,驱动电流会自动调节。专用转换率控制用于降低栅极驱动EMI值。GD30DR8306可以在4.5V到30V单电源下工作。这个装置与一个支持100%占空比的可调节电荷泵相结合,从而提供门极驱动电流和内部LDO。 1、电压4.5-30V宽压供电; 2、可编程序的门极驱动电流,峰值1A灌流和1.2A拉电流; 3、智能化的高端低端压摆控制; 4、PWM输入控制高可达200kHz; 5、可选择2个PWM模式(6x和3x); 6、内置5V/2ADC-DC电压降控制器; 7、3.3V和5V数字接口; 8、整合5VLDO; 9、散热增强:QFN32(5x5); 10、保护职能: --死区时间插入; --MOSFET直通保护; --过温保护; --故障诊断; --VDD欠压闭锁(UVLO); 成功案例: GD32F303+GD30DR8306。 配置1650中空杯型无刷马达。 电源电压:锂电池7.4V,锂电池11.1V。 速度:100~30000rpm。 控制模式:无霍尔FOC/无霍尔方波。 这个方案的主要特征: 1、所用的以gd芯片代理商GD30DR8306驱动芯片将3个开关二极管集成在一起,例如IN4148,1个5VLDO,1个DC-DCBuck控制器,使得外围电路元件大大减少,节省了PCB空间,降低了BOM成本。 2、使用完全的NMOSFET,一致性好,稳定性好。与传统的P+NMOSFET电路设计相比,由于PMOSFET和NMOSFET的Rdson阻值有较大差别,PMOSFET的管道速度比N慢,在弦波控制/或方波调速时很难做到均衡。 3、利用FOC算法控制中空杯无感电机,具有良好的动态性、低噪声、高效率、长寿命及良好的使用体验。
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02
2021-12

RTG起重机雷达传感器防撞装置轮胎式龙门起重机防撞领域应用

发布时间: : 2021-12--02
RTG起重机雷达传感器防撞装置轮胎式龙门起重机防撞领域应用,轮胎式龙门起重机(rubber-tyredgantrycrane,RTG)是专业化集装箱码头堆场中的主要作业机械。在堆场设备稠密的环境中,随着作业箱数的增加,设备防撞防护显得尤为重要。在堆场设备防撞器中,目前主要采用超声波和激光传感器。这两种测距离防撞器都容易受到光、噪声、雨雪等环境的影响,出现频率误报,实际使用效果不佳。为保证RTG作业安全性,在充分调研市场的基础上,研制了雷达传感器进行RTG防撞。雷达感应器不受光、噪音、雨雪等环境的影响,性能更可靠,能有效地防止RTG间和RTG车间的碰撞。 1、雷达传感器在RTG防撞领域的应用研究 在RTG防撞领域中应用的传感器应符合探测距离不小于20m、减速区、停车范围可调、反应时间不超过0.5s、直接与可编程序逻辑控制器的输入输出端连接。环境因素如积雪、雾气、冰雹、强光等。由于采用了广泛的24GHzFM连续波技术,该技术在RTG防撞领域的适用性主要体现在: (1)能实时检测到探测区域内的静止及移动目标; (2)支持20米的探测距离; (3)发出警报(红色),警报(黄色)、信息(绿色)等3个可单独设置的警报区域; (4)具有非常正确而灵活的可配置区域(1.8~20.0m); (5)3种继电器输出; (6)可以通过计算机软件对其进行配置,并且可以通过通用的串行总线接口进行各种调节和配置。 根据雷达波探测的特点,雷达传感器不仅能防止RTG间的碰撞,还能检测RTG前方障碍物和人员,具有广泛的防护范围。利用雷达传感器进行有效挖掘,可以弥补港口机械测距和激光测距所存在的不足。 2、雷达传感器与RTG的安装与应用 常规RTG防撞器一般安装在主梁上方,以降低干扰源,因此,它只能防止RTG之间的碰撞,也不能阻止RTG与其车道上的障碍物碰撞。根据雷达传感器具有满足多种保护要求的特点,把它装入RTG大轮位置,可同时防止RTG机箱和RTG机箱之间的碰撞,极大地节约了集装箱码头的防撞费用。在RTG大车护栏距地面约1.5m处安装雷达传感器,扫描范围为水平7°(可调),垂直28°(可调)。当前,大多数港口已经实行RTG“油改电”,采用滑触线供电,因此,在RTG防撞领域,城市电滑触线防护尤其重要。RTG雷达传感器证明:车道侧滑触线柱、正常堆叠集装箱(包括普通集装箱和冷藏集装箱)及地面杂波都不会使雷达传感器发出错误的减速或停止信号;当RTG逐渐靠近前方RTG时,雷达感应器发出正确的减速或停止信号,20m的探测距离可保证RTG有足够的减速或停止反应距离;雷达传感器能准确地探测车道内的工作人员,并控制RTG及时制动;如果集卡在规定的白线区域内,那么雷达传感器就不会发出引起RTG误动的信号;如果集卡驶出,或者它的尾挂盘在白线区域之外,雷达传感器就可以正确地探测到它的距离,并控制RTG减速或停止。 3、雷达传感器在RTG防撞方面的应用效果 通过对RTG防撞系统的实际应用,雷达传感器具有超声波或激光传感器的测距功能,适用于RTG间防撞和RTG防撞两种工况,并且不受暴雨、强风、高温等环境因素的影响,使用效果良好。雷达传感器具有远距离、高抗干扰性好等优点,因此,雷达防撞器作为RTG大车辅助安全防护装置,在未来提升机自动化操作领域中起着重要作用。
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02
2021-12

乐鑫wifi模块代理商ESP32的IoT心电监测应用智能扬声器荣获AlexaVoxCon年度创新奖

发布时间: : 2021-12--02
乐鑫wifi模块代理商ESP32的IoT心电监测应用智能扬声器荣获AlexaVoxCon年度创新奖,应用ESP32进行IoT心电监测,AlexNewton提供了一个基于ESP32的IoT心电监测(ECG)教程,它显示远程心脏监测可以在医生和病人无论之间有多远。 心脏疾病不可忽视。对病患进行早期心电图(ECG)信号的监测和分析,可防止心脏病的恶化。ECG是一种心电信号,它能为判断病人心脏状况、诊断病人心律失常.起搏功能.心衰等提供重要信息。采用AD8232传感器和乐鑫wifi模块代理商ESP32的IoT心电监测产品并非医疗设备,也并非打算用作医疗设备,但它展示了如何利用物联网来改进病人的心脏监测。此外,该项目还显示,IoT技术能够将医生和偏远地区的病人隔离开来,医生可以远程在线监控来自患者心脏的心电信号。‘ 该项目要求的组成部分如下: 1、AD8232心电传感器及电极 2、乐鑫wifi模块代理商ESP32 3、一种带有小型USB接口的5V适配器电源 AlexNewton的教程展示如何在任何IoT云平台上监控同样的心电图。一个是AD8232心电传感器需要与ESP32相连。心电图就会连接到患者胸部或手,产生ECG信号。使用Ubidots参数(比如API键或标记),心电图可以通过MQTTBroker向云发送。AD8232心电传感器是一种经济有效地测量心电活动的PCB板。设计的初衷是采集噪声(如由于移动或远距离电极产生的噪声等),可放大并过滤微弱的生物电信号。由于AD8232单引心率监测仪像运放器一样,能很容易地得到清晰的心脏信号。 ESP32可以通过它的SPI/SDIO或I2C/UART接口连接到这样的系统,提供Wi-Fi和蓝牙功能。AD8232心电传感器项目采用的乐鑫wifi模块代理商ESP32模块为ESP32-WROOM-32。这个模块包含了ESP32芯片、Flash闪存器、高精度分立元件,和拥有良好RF性能的PCB天线。 根据线路图,将AD8232心电传感器与ESP32-WROOM-32连接,该模块供电电压为3.3V。GND随后被连接到GND。AD8232的输出管脚是模拟信号,它与ESP32-WROOM-32的VP管脚相连。与此类似,AD8232上的LO+和LO-针应分别在ESP32-WROOM-32上与D2和D3插针相连。同时,我们也需要像Ubidots这样的物联网平台来把数据放到云端,使开发者很容易地获得传感器数据,并将其转换成有用的信息。 ESP32智能扬声器荣获AlexaVoxCon“年度创新奖”,乐鑫的合作公司SirenaTechnologies推出了基于乐鑫ESP32和ESP32-LyraTD-DSPG设计的智能语音产品,并在印度获得了AlexaVoxCon的年度创新奖。 AlexaVoxConConference,印度首都新德里,音乐合作公司SirenaTechnologiesPrivateLimited获得了“Alexa语音服务”(AlexaVoiceService)又称AVS年度佳创新奖。优胜者AlexaAdaptor和SmartSpeaker均采用乐鑫wifi模块代理商ESP32芯片和ESP32-LyraTD-DSPG音频开发板作为参考设计。基于乐鑫ESP32和乐鑫ESP-IDF操作系统的参考设计相比,采用的BOM数量很少,大大降低了设计智能音箱的成本,并减少了投入市场的时间。 亚马逊推出的一款智能助手Alexa可以进行语音交互、音乐播放、制作任务清单、设置闹铃、流媒体播客、播放有声书,并提供天气、交通、体育和其他实时信息。Alexa语音服务允许开发人员通过话筒和扬声器向连接的产品提供语音功能。整合后,您的产品将能够使用上述Alexa内建功能,并可以使用Alexa技能工具箱开发第三方技能。SirenaTechnologies基于Alexa设计的智能语音产品AlexaAdaptor和SmartSpeaker采用乐鑫wifi模块代理商ESP32-LyraTD-DSPG音频开发板,搭配DBMD5PDSP芯片,3麦克风。除具有Alexa的多轮对话.音乐流媒体服务.设置闹钟、代办提醒等功能外,AlexaAdaptor也支持外接功放器来播放音频,音乐的流媒体可以通过本地扬声器播放;SmartSpeaker也能用智能手机播放本地音乐。 乐鑫ESP32芯片接入了Alexa语音服务,并且支持所有的LyraT开发板。其中的核心ESP32-LyraTD-DSPG是一款与DBMD5PDSP芯片配套使用的乐鑫wifi模块代理商ESP32芯片的乐鑫音频开发板。它具有消声回波(AEC)功能,适用于语音识别、近、远场语音唤醒等应用场景,可对WAV、MP3、AAC、FLAC、OPUS和OGG等多种音频文件格式进行无损编码/解码。这款开发版也支持与亚马逊的AVS(Alexa语音服务)相连接、谷歌的Dialogflow和谷歌语音助手GVA。
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01
2021-12

AI人机智能穿戴无线交互式雷达传感器物体移动接近远离感应手势识别

发布时间: : 2021-12--01
AI人机智能穿戴无线交互式雷达传感器物体移动接近远离感应手势识别,人机交互技术作为人工智能(AI)的一大技术基础,随着近十年的不断突破,人类-计算机交互(HCI)逐渐成为人类-机器交互(HCI)的发展,其更高效率的传感技术迎来了巨大的市场需求。在人-机交互过程中需要大量的传感器,高清晰摄像机、声音传感器、毫米波雷达传感器、电容感应器、近程传感器、红外线传感器等,它们都可以用来探测外部环境和物体的反应。伴随着半导体技术的发展和微波/毫米波集成电路(MMIC)技术的发展,毫米波传感器在人机交互中的应用逐渐成为现实。目前,全球的主要公司已经开始开发毫米波交互技术,比如,德国的英飞凌(Infineon)和美国的Google等。毫米波雷达传感器有很宽的带宽,能够非常正确地检测并反馈信息,例如某些物体的移动或手势的改变。在此基础上,毫米波传感器被用来对可穿戴设备进行手势控制,以检测用户接近、远离或改变姿势。 可穿戴的毫米波人机交互技术构想,人-机交互经历了鼠标到多点触控阶段,发展到目前流行的体感技术。就其发展趋势而言,可穿戴设备人机交互技术能够通过毫米波雷达传感器感知人体的动作(姿势、姿态、距离、速度、加速度等),虚拟用户表达模块经过信号采集、处理、理解和管理后,与计算机进行交互式对话,可以大大提高用户的交互体验,不仅仅是体感游戏,更重要的是将来学习、工程训练、机械操作、运动训练等许多场合,都有很好的应用前景。相对于红外线等光学人机交互技术,采用毫米波雷达传感器的人机交互技术具有以下优势:(1)毫米波人机交互技术具有更好的抗干扰能力;(2)毫米波不依赖自然光、不分昼夜、不分昼夜、具有良好的全天候工作特性;(3)毫米波雷达通过计算相移,(4)利用极低的计算量获得目标的运动特性;(4)基于人机交互技术的毫米波雷达传感器在商业应用中有其优点。(5)毫米波对塑料、砖、板等材料具有良好的穿透性,可用于某些特殊场合。单频率连续波(CW)和FMCW型式的毫米波雷达传感器是由周期直流或三角/锯齿波函数调制的。被调制发射的雷达信号从目标反射/散射回接收器后就产生了时间、频率和相位的差异,其中,时间延迟就是毫米波往返的时间;可用于计算目标的距离;频率变化是由物体的相对运动引起的多普勒效应,可用来计算目标的速度;相位的差别是物体相对波前阵面的位置差;可用于计算目标方位。将接收器信号与发送器信号进行参数化,减去静止不变的背景环境噪声,可得到表示目标特征的各种信号参数。 在FMCW模式雷达中,调制波形为锯齿波,连续波(CW)模式为常数电平。CW/FMCW双模式毫米波雷达的传感设计了一种应用于人机交互的毫米波雷达传感器,采用两种雷达共用一个雷达前端,CW和FMCW两种雷达系统的切换控制。采用时域分离的方法,将VCO通过单刀双抛开关(SPDT)开关(SPDT),将VCO分别装入两种不同的调制信号(恒定或锯齿波),并对相应的中频信号处理电路进行处理。该雷达工作于CW模式,调制波形为一个正常电常数,而调制波形为锯齿波时,雷达工作于FMCW模式。整体雷达的前端主要包括天线单元、射频单元、中频信号处理器。外部电路包括波形发生器(WaveGenerator)、电源供电单元、数模转换(DA)单元、数字信号处理(DSP)等。几个雷达前端呈线形排列,与周边电路单元构成一套完整的人机交互应用的毫米波传感器组件系统。雷达头发射毫米波,把接收回波转换成中频信号,再经中频信号处理单元放大、滤波,再由数字信号处理单元采集中频信号,再进行数字信号处理,分析得到人体三维运动特征信息。再将控制信号输出到中频信号处理器,使中频处理单元可根据雷达工作方式选择相应的中频信号处理电路。该天线采用平面微带阵列天线,发射4个单元,接收4个单元。该雷达采用中央控制器,控制3台SPDT,选择相应的调制波形和中频信号处理电路。CW工作方式中,雷达中频信号的处理电路经过LPF滤波后,再进行特征识别,FMCW工作模式下的雷达中频信号处理电路进行特征识别。 毫米波雷达传感器的测试结果是对毫米波雷达传感器进行人体静息和运动模拟测试。通过将中频滤波器的滤波带宽调谐到50kHz-100kHz,使得雷达只能探测7m到10m范围内的人体静止和运动;但对于其它距离的目标运动信号,当双模雷达处于FMCW模式下,它能很好地检测和识别目标距离为7m~10m的人体静止状态,利用CW模式下的常数调制雷达,在雷达距离为9m处向雷达走来,速度由慢向快,中频信号具有较好的频谱变化。通过对信号的后期处理和目标特征识别算法,可以较好地对人体姿态特征进行识别,实现人体可穿戴设备的无线交互功能。 对可穿戴设备无线应用的毫米波传感器技术进行了研究,以MMIC技术为基础,设计了CW/FMCW双模毫米波雷达传感器,并对人体运动进行了简单测试。传感可以很好的用于人体运动的识别,但是在后续的信号处理、特征识别、算法优化等方面仍有待改进。在三维体感游戏中运用了毫米波人技术,能在三维空间正确地对人体的各种运动进行数学建模,为了让3D体感游戏更正确、更有仿真的3D体感游戏,特征识别、信号处理、算法学习、特征识别和无线互连,与此同时,降低大型3D体感游戏的装备成本,使3D体感游戏技术更加普及、普及。
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01
2021-12

兆易创新gd代理商电源管理GD30LD330xLDO芯片工业GD30DR8306电机驱动开发平台

发布时间: : 2021-12--01
兆易创新gd代理商电源管理GD30LD330xLDO芯片工业GD30DR8306电机驱动开发平台,电源管理行业需求深度挖掘GD30LD330xLDO芯片详细说明。功率管理芯片在几乎所有的电子产品和设备上都有应用,如便携式产品、数字消费电子产品、计算机、通讯网络设备、工业设备、汽车电子等。在这些芯片中,消费电子是大的功率管理芯片。随着中国大陆移动设备产能的进一步扩大,消费类电子产品的电源管理芯片也迅速增长,增长幅度在13.7%左右。近年来,新能源汽车产业迅速崛起,这也促使汽车电子领域功率管理芯片快速增长,市场占有率显著提高。根据统计,2020年国内电源管理芯片的市场规模已达790.1亿元,2021年有望突破800亿元,达到844.3亿元。 低电压线性稳压器(lowdropoutput)是一种线性降压型电源管理芯片,它是中国电源管理芯片需求大的单一产品,占19.3%,在电源开关方面深受电子市场的青睐。LDO芯片同样受到电子工程师们的青睐,它以其低成本、低噪声、低电流等特点,在电子市场上占有重要地位。那到底LDO芯片的特点和优点是什么呢? LDO芯片有较好的降压稳压效果。如果有大量的输入,输出基本上是稳定的。其次,LDO芯片上的一项重要指标是PSRR(电源电压噪声抑制系数),输入电源的噪声通过LDO芯片可以产生良好的抑制效果。再次,通过LDO芯片电路,可以滤除绝大多数无用的转换信号,具有很好的滤波效果。有一种LDO芯片,可调节输出电压,用户可根据不同的应用场景选择合适的LDO芯片。 Memorial公司推出的LDO芯片GD30LD3300/3301是一款高性能、低噪声、低电压降的线性稳压器,具有高PSRR,高抗噪;集成欠压锁定、软启动控制和多种保护功能。这种LDO芯片主要应用于无线基础设施、通信网络和工业应用等。该成果对兆易创新LDO芯片领域具有重大突破,丰富了GD30PMU系列产品。 GD30LD3300/3301xLDO概述。兆易创新gd代理商GD30LD3300/3301是两种低噪声低压降线性稳压(LDO),能提供3A负载电流,其大压降只有180mV同时采用了低噪声、高功率抑制比和高输出电流特性的组合,适合高速通信、射频、医疗等噪声敏感领域。通过设置内部引脚(Pin-setting)和外部电阻(Externalresistancesetting)两种方法来调节器件的输出电压。 GD30LD3300采用Pin-setting,输出电压在0.5~2.075V之间,通过Externalresistancesetting输出电压可达0.5V~5.2V。GD30LD3301采用Pin-setting,输出电压0.8V~3.95V,步长50mV,通过Externalresistancesetting输出电压0.8V~5.2V。就特定用途集成电路(ASIC)而言,现场可编程门阵列(FPGA)和一些特殊应用要求的低输入低输出(LILO)状态,兆易创新gd代理商GD30LD3300/3301可以通过提供BIAS偏压实现。 兆易创新gd代理商GD30LD3300/3301x主特性。 1、输入电压范围大 没有BIAS偏压:1.4V~6.5V。 BIAS偏压:1.1V~6.5V。 2、高精度的输出电压 GD30LD3300。 Pin-setting:0.5V~2.075V。 Externalresistancesetting:0.5V~5.2V。 GD30LD3301。 Pin-setting:0.8V~3.95V。 Externalresistancesetting:0.8V~5.2V。 两者的输出电压精度均为±1%。 3、UltraLowDropoutVoltage。 在3A输出的情况下,大压差只有180mV。 4、UltraHighPSRR。 42dBat10KHz和39dBat500KHz 5、 Excellent Noise Immunity 5.9uVRMSat0.8VOutput 9.8uVRMSat5VOutput。 6、UVLO 欠压锁(UVLO)电路在输入或偏置电源到达小工作电压范围前,确保设备在输入或偏置电源崩溃时仍处于停用状态。 7、PowerGoodIndicator。 GD30LD3300/3301内部的PowerGood电路可以监控反馈管脚上的电压,以指示输出电压的状态。 8、“软起动”控制功能。 兆易创新gd代理商GD30LD3300/3301具有软启动控制功能,通过外电容CNR/SS设定,可在启动过程中减小大浪涌电流,有效地避免了电压过冲。 9、保护功能 多种保护功能,如短路、过流、过温。 兆易创新为各系列电源管理产品配备了完整的软、硬件配套资料,包括开发板、配套示意图、使用指南等,为用户的开发、调试提供了便利。 新GD30DR8306电机驱动开发平台,推动工业4.0创新。在工业领域,电动机是动力来源。电能与动能是通过电与磁相互作用而相互转化的。电动机在世界范围内占有举足轻重的地位,其应用范围广泛,如信息处理、音响设备、汽车电器、航空航天、工农业生产等各领域。 近年来,随着无人驾驶、智能机器人、智能家电和汽车电子市场的兴起,驱动和控制领域的市场潜力逐步得到释放,电机控制器市场规模逐年扩大。据《中国电机控制器产业数据2020年度发展研究报告》,2019年电机控制器行业市场规模达2400亿元,2011-2019年市场增长率保持10%以上。预期未来一段时期仍将保持较好的发展势头。 电动机控制器作为电池组和电机之间的连接转换单元,是电机传动和控制系统的核心,其重要性不言而喻。在日益扩大的市场需求下,对电机驱动技术和控制器性能的要求日益提高。电机系统数字化是未来的必然趋势。基于高性能高速处理器的电驱动控制系统,可实现复杂多变的控制算法,进一步提高电机效率。第二,电动机系统的轻量化与一体化也是大势所趋。就控制器而言,实现功率器件、驱动、控制、传感器、电源等的集成化,不仅减小了体积,而且有利于提高电机系统效率,减少能耗损失。 兆易创新gd代理商GD30DR8306驱动芯片,具有电机驱动、保护、LDO、BUCK等多种功能,与GD32E230系列MCU相匹配,研制了GD32E230C-FOC电机驱动参考设计,为电机驱动领域迈出了一大步。 介绍GD32E230C-FOC。GD32E230C-FOC是一款电动机驱动的开发平台,GigaDeviceGD32E230C8T6芯片,采用Cortex®-M23内核,采用GD30DR8306作为驱动芯片,完成了电机驱动功能。GD30DR8306x是一种三相门驱动装置,可配置DC/DC降压控制器。驱动装置包括三个半桥驱动器,每个驱动器可以驱动两个NMOSFET,并支持高达1.2A的电流和1A的灌流电流。驱动装置在一个固定的死时间内插入,防止了高低侧的MOSFET在切换时发生短路。 GD32E230C-FOC可以通过按键开关和拨号开关来控制电动机(模式选择、启停、制动、转向等),1.3寸OLED液晶显示器的工作状态,实现多种定位算法。此面板提供船型电源开关、SWD接口、回位键、旋钮编码器、电机接口、USART调试口等外部资源,可实现过压/欠压检测,过流检测等保护功能。 兆易创新gd代理商GD32E230C-FOC支持BLDC或PMSM电机,电压4.5V-30V,流量限制2A。电机控制采用状态机机制,电机状态主要为INIT(初始)、IDLE(闲置)、RUNNING(运行)、图中BRAKE(制动器)和FAULT(错)5种,电机控制状态机具体切换过程如图状态控制机所示,只要满足相应条件就可进行电机控制状态切换。利用状态机机理对电机控制进行管理,使控制过程清晰,效率高。 GD32E230C-FOC特性 1.GD32E230C-FOC电机驱动开发平台特性: 1)FOC向量控制系统; 2)SVPWM调制技术支持七段、五段实现模式; 3)支持三电阻和一阻流采样; 4)支持有感(HALL/递增编码器)定位方式和无感觉(Runnberg/super)定位方式; 5)支持HALL,自动识别编码器偏移角度; 6)超压,欠压和过流检测和保护电路; 7)1.3寸OLED屏实现电机控制,工作参数显示,FAULT状态报警显示; 8)旋钮编码器开关EC11调速; 9)键实现模式选择、启动、制动等功能; 2.GD30DR8306xPMU主要规格说明: 1)电源电压4.5-30V; 2)可编程序门极驱动电流,峰值1A源极和1.2A灌流; 3)高精度、低端摆率控制; 4)PWM输入控制高可达200kHz; 5)PWM模式2(6x和3x); 6)内置5V/2ADC-DC电压降控制器; 7)3.3V和5V数字接口; 8)整合5VLDO; 9)散热增强:QFN32(5x5); 10)保护职能: 11)插入死区时间; 12)MOSFET直通保护; 13)防止温度过高; 14)故障诊断; 15)VP和VDD欠压锁(UVLO); 3.GD32E230系列MCU主要规格说明: 1)ArmCortex-M23@72MHz,55DMIPS的处理性能; 2)Flash:64KB/32KB/16KB; 3)SRAM:8KB/6KB/4KB; 4)12BitsADCx1@2.6Msps,高速高精度ADC10通道; 5)先进的计时器x1,可以产生6路死区可调的互补PWM输出; 6)普通计时器x5; 7)闪光灯具有硬件加密保护; 8)多种串行通信:I2Cx2、SPIx2、UARTx2; 9)包装种类丰富:TSSOP20/LGA20/QFN28/QFN32/LQFP32/LQFP48; 10)电源电压:1.8V~3.6V; 11)工业级工作温度范围:-40℃~+85℃; 12)工业级ESD特性:6000伏特; 4.说明马达的参数: (本平台选择常州精控电机为例,具体参数如下) 机型:常州精控电机JK57BLS02型PMSM电机; 三相绕组接线顺序:U(黄)V(绿)W(蓝); 终端:+5V(红色)GND(黑)A(黄)B(绿)C(蓝); 极数:四极; 电阻值:0.33Ω; 标定电压:DC24V; 扭矩额定值:0.22N·M; 车速:3000±10%RPM; 转速:3800±10%RPM; 无负载电流:0.7安培; 出力:69W; 反电势常数:6.3V/KRPM; 转矩系数:0.06N·M/A; 绝热层:ClassB; 绕线方式:星型式; 优点GD32E230C-FOC: 1.驱动电压范围广。 GD30DR8306x支持4.5-30V宽电压输入,可满足不同的解决方案。 2.LDO输出容量高。 GD30DR8306x自带的LDO支持5.0V/40mA的输出,并能装载一些外部设备,同时保证驱动芯片正常工作。 3.BUCK线路的可选。 GD30DR8306x内置一个DC/DC降压力器,驱动外部高端N通道MOSFET,提供2A输出电流,输出可调至5V。 4.驱动电流。 可编程序的栅极驱动电流,能承受1A的峰值电流和1.2A的灌流。 5.高频PWM控制。 GD30DR8306x支持200KHzPWM输入控制。 6.支持多种算法。 GD32E230C-FOC支持HALL、ENCODER、LUENBURGER和SMO四个控制程序。 7.多种保护性。 支持过热保护,故障诊断,VP和VDD欠压锁定,整个系统支持输入过压、欠压、过流等多种保护。 浏览飞睿科技兆易创新gd代理商网站和遍及各地的销售和技术支持网络,你可以更深入地了解和利用GD32系列产品的特性和特性。在你进行设计之前,会发现GD32智能创新解决方案有很多优点。
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