这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F207ZCT6-GD32 ARM Cortex-M3 Microcontroller

兆易创新GD32F207ZCT6-GD32 ARM Cortex-M3 Microcontroller GigaDevice Semiconductor Inc. GD32F207xx ARM® Cortex®-M3 32-bit MCU Datasheet General description The GD32F207xx device belongs to the performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best cost-performance ratio in terms of processing capacity, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F207xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, a USBFS and an Ethernet. Additional peripherals as TFT-LCD Interface (TLI), EXMC interface with SDRAM extension support, Digital camera interface (DCI), Cryptographic acceleration unit (CAU), Hash acceleration unit (HAU), True random number generator (TRNG) are included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F207xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, POS and electronic payment, automotive navigation and so on. Device information Table 2-1. GD32F207xx devices features and peripheral list   Part Number GD32F207xx   RC RE RG RK VC VE VG VK Flash Fast area (KB) 256 512 384 384 256 512 384 384   Normal area (KB) 0 0 640 2688 0 0 640 2688   Total (KB) 256 512 1024 3072 256 512 1024 3072 SRAM (KB) 128 128 256 256 128 128 256 256 Timers General timer(16- bit) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13) 10 (1-4,8-13)   Advanced timer (16-bit) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7) 2 (0,7)   SysTick 1 1 1 1 1 1 1 1   Basic timer (16- bit) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6) 2 (5,6)   Watchdog 2 2 2 2 2 2 2 2   RTC 1 1 1 1 1 1 1 1 Connectivity USART 4 4 4 4 4 4 4 4     UART 2 (3-4) 2 (3-4) 2 (3-4) 2 (3-4) 4 (3-4,6-7) 4 (3-4,6-7) 4 (3-4,6-7) 4 (3-4,6-7)   I2C 3 3 3 3 3 3 3 3     SPI/I2S 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2) 3/2 (0-2)/(1-2)
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F207ZCT6-GD32 ARM Cortex-M3 Microcontroller

GigaDevice Semiconductor Inc.
GD32F207xx
ARM® Cortex®-M3 32-bit MCU
Datasheet

General description

The GD32F207xx device belongs to the performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best cost-performance ratio in terms of processing capacity, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F207xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, a USBFS and an Ethernet. Additional peripherals as TFT-LCD Interface (TLI), EXMC interface with SDRAM extension support, Digital camera interface (DCI), Cryptographic acceleration unit (CAU), Hash acceleration unit (HAU), True random number generator (TRNG) are included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications.
The above features make GD32F207xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, POS and electronic payment, automotive navigation and so on.

Device information

Table 2-1. GD32F207xx devices features and peripheral list

 

Part Number

GD32F207xx

 

RC

RE

RG

RK

VC

VE

VG

VK

Flash

Fast area (KB)

256

512

384

384

256

512

384

384

 

Normal area (KB)

0

0

640

2688

0

0

640

2688

 

Total (KB)

256

512

1024

3072

256

512

1024

3072

SRAM (KB)

128

128

256

256

128

128

256

256

Timers

General timer(16-

bit)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

 

Advanced timer

(16-bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

1

1

1

1

 

Basic timer (16-

bit)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

 

Watchdog

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

Connectivity

USART

4

4

4

4

4

4

4

4

 

 

UART

2

(3-4)

2

(3-4)

2

(3-4)

2

(3-4)

4

(3-4,6-7)

4

(3-4,6-7)

4

(3-4,6-7)

4

(3-4,6-7)

 

I2C

3

3

3

3

3

3

3

3

 

 

SPI/I2S

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

3/2

(0-2)/(1-2)

 

SDIO

1

1

1

1

1

1

1

1

 

CAN

2

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

1

 

ENET

1

1

1

1

1

1

1

1

 

TLI

0

0

0

0

1

1

1

1

 

DCI

1

1

1

1

1

1

1

1

 

CAU/HAU

1

1

1

1

1

1

1

1

GPIO

51

51

51

51

82

82

82

82

EXMC/SDRAM

0/0

0/0

0/0

0/0

1/0

1/0

1/0

1/0

 

 

Part Number

GD32F207xx

 

RC

RE

RG

RK

VC

VE

VG

VK

ADC (CHs)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

3(16)

DAC

2

2

2

2

2

2

2

2

Package

LQFP64

LQFP100

 

 

Part Number

GD32F207xx

 

ZC

ZE

ZG

ZK

IE

IG

IK

Flash

Code area (KB)

256

512

384

384

512

384

384

 

Data area (KB)

0

0

640

2688

0

640

2688

 

Total (KB)

256

512

1024

3072

512

1024

3072

SRAM (KB)

128

128

256

256

128

256

256

Timers

General timer

(16-bit)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

10

(1-4,8-13)

 

Advanced timer

(16-bit)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

2

(0,7)

 

SysTick

1

1

1

1

1

1

1

 

Basic timer (16-

bit)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

2

(5,6)

 

Watchdog

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

Connectivity

USART

4

4

4

4

4

4

4

 

UART

4

4

4

4

4

4

4

 

I2C

3

3

3

3

3

3

3

 

SPI/I2S

3/2

3/2

3/2

3/2

3/2

3/2

3/2

 

SDIO

1

1

1

1

1

1

1

 

CAN

2

2

2

2

2

2

2

 

USBFS

1

1

1

1

1

1

1

 

ENET

1

1

1

1

1

1

1

 

TLI

1

1

1

1

1

1

1

 

DCI

1

1

1

1

1

1

1

 

CAU/HAU

1

1

1

1

1

1

1

GPIO

114

114

114

114

140

140

140

 

 

Part Number

GD32F207xx

 

ZC

ZE

ZG

ZK

IE

IG

IK

EXMC/SDRAM

1/1

1/1

1/1

1/1

1/1

1/1

1/1

ADC (CHs)

3(24)

3(24)

3(24)

3(24)

3(24)

3(24)

3(24)

DAC

2

2

2

2

2

2

2

Package

LQFP144

LQFP176

Memory map

Table 2-2. GD32F207xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

External Device

 

 

 

AHB

0xC000 0000 - 0xDFFF FFFF

EXMC - SDRAM

 

 

0xA000 1000 - 0xBFFF FFFF

Reserved

 

 

0xA000 0000 - 0xA000 0FFF

EXMC - SWREG

 

External RAM

 

0x9000 0000 - 0x9FFF FFFF

EXMC - PC CARD

 

 

0x7000 0000 - 0x8FFF FFFF

EXMC - NAND

 

 

0x6000 0000 - 0x6FFF FFFF

EXMC - NOR/PSRAM/SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

 

 

AHB2

0x5006 0C00 - 0x5FFF FFFF

Reserved

 

 

0x5006 0800 - 0x5006 0BFF

TRNG

 

 

0x 5006 0400 – 0x5006 07FF

HAU

 

 

0x 5006 0000 – 0x5006 03FF

CAU

 

 

0x5005 0400 - 0x5005 FFFF

Reserved

 

 

0x5005 0000 - 0x5005 03FF

DCI

 

 

0x5004 0000 - 0x5004 FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

AHB1

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

0x4002 A000 - 0x4FFF FFFF

Reserved

 

 

0x4002 8000 - 0x4002 9FFF

ENET

 

 

0x4002 3400 - 0x4002 7FFF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1400 - 0x4002 1FFF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0800 - 0x4002 0FFF

Reserved

 

 

0x4002 0400 - 0x4002 07FF

DMA0

 

 

0x4002 0000 - 0x4002 03FF

DMA1

 

 

0x4001 8400 - 0x4001 FFFF

Reserved

 

 

0x4001 8000 - 0x4001 83FF

SDIO

 

 

 

 

 

 

 

APB2

0x4001 7C00 - 0x4001 7FFF

Reserved

 

 

0x4001 7800 - 0x4001 7BFF

GPIOI

 

 

0x4001 7400 - 0x4001 77FF

GPIOH

 

 

0x4001 7000 - 0x4001 73FF

USART5

 

 

0x4001 6C00 - 0x4001 6FFF

Reserved

 

 

0x4001 6800 - 0x4001 6BFF

TLI

 

 

0x4001 5800 - 0x4001 67FF

Reserved

 

 

0x4001 5400 - 0x4001 57FF

TIMER10

 

 

0x4001 5000 - 0x4001 53FF

TIMER9

 

 

0x4001 4C00 - 0x4001 4FFF

TIMER8

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 4000 - 0x4001 4BFF

Reserved

 

 

0x4001 3C00 - 0x4001 3FFF

ADC2

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

TIMER7

 

 

0x4001 3000 - 0x4001 33FF

SPI0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

ADC1

 

 

0x4001 2400 - 0x4001 27FF

ADC0

 

 

0x4001 2000 - 0x4001 23FF

GPIOG

 

 

0x4001 1C00 - 0x4001 1FFF

GPIOF

 

 

0x4001 1800 - 0x4001 1BFF

GPIOE

 

 

0x4001 1400 - 0x4001 17FF

GPIOD

 

 

0x4001 1000 - 0x4001 13FF

GPIOC

 

 

0x4001 0C00 - 0x4001 0FFF

GPIOB

 

 

0x4001 0800 - 0x4001 0BFF

GPIOA

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

AFIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 C400 - 0x4000 FFFF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

I2C2

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

UART7

 

 

0x4000 7800 - 0x4000 7BFF

UART6

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6C00 - 0x4000 6FFF

BKP

 

 

0x4000 6800 - 0x4000 6BFF

CAN1

 

 

0x4000 6400 - 0x4000 67FF

CAN0

 

 

0x4000 5C00 - 0x4000 63FF

USB/CAN shared

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 5000 - 0x4000 53FF

UART4

 

 

0x4000 4C00 - 0x4000 4FFF

UART3

 

 

0x4000 4800 - 0x4000 4BFF

USART2

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

SPI2/I2S2

 

 

0x4000 3800 - 0x4000 3BFF

SPI1/I2S1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1C00 - 0x4000 1FFF

TIMER12

 

 

0x4000 1800 - 0x4000 1BFF

TIMER11

 

 

0x4000 1400 - 0x4000 17FF

TIMER6

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0C00 - 0x4000 0FFF

TIMER4

 

 

0x4000 0800 - 0x4000 0BFF

TIMER3

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

 

SRAM

 

 

AHB

0x2004 0000 - 0x3FFF FFFF

Reserved

 

 

0x2002 0000 - 0x2003 FFFF

SRAM2(128KB)

 

 

0x2001 C000 - 0x2001 FFFF

SRAM1(16KB)

 

 

0x2000 0000 - 0x2001 BFFF

SRAM0(112KB)

 

 

 

 

 

Code

 

 

 

 

 

AHB

0x1FFF F810 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF F80F

Option Bytes

 

 

0x1FFF B000 - 0x1FFF F7FF

System memory

 

 

0x0830 0000 - 0x1FFF AFFF

Reserved

 

 

0x0800 0000 - 0x082F FFFF

Main Flash(3072KB)

 

 

 

0x0000 0000 - 0x07FF FFFF

Aliased to Flash or system memory according to BOOT

pins configuration

GD32F207Ix LQFP176 pin definitions

Table 2-3. GD32F207Ix LQFP176 pin definitions

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PE2

 

1

 

I/O

 

5VT

Default: PE2

Alternate: TRACECK, EXMC_A23 Remap: ENET_MII_TXD3

 

PE3

 

2

 

I/O

 

5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

 

PE4

 

3

 

I/O

 

5VT

Default: PE4

Alternate:TRACED1, EXMC_A20 Remap: DCI_D4, TLI_B0

 

PE5

 

4

 

I/O

 

5VT

Default: PE5 Alternate:TRACED2, EXMC_A21

Remap: TIMER8_CH0, DCI_D6, TLI_G0

 

PE6

 

5

 

I/O

 

5VT

Default: PE6 Alternate:TRACED3, EXMC_A22

Remap: TIMER8_CH1, DCI_D7, TLI_G1

VBAT

6

P

 

Default: VBAT

PI8

7

I/O

 

Default: PI8

PC13- TAMPE R-RTC

 

8

 

I/O

 

5VT

 

Default: PC13

Alternate: TAMPER-RTC

PC14- OSC32

IN

 

9

 

I/O

 

 

Default: PC14 Alternate: OSC32IN

PC15- OSC32

OUT

 

10

 

I/O

 

 

Default: PC15 Alternate: OSC32OUT

 

PI9

 

11

 

I/O

 

5VT

Default: PI9

Alternate: EXMC_D30

Remap: TLI_VSYNC, CAN0_RX

 

PI10

 

12

 

I/O

 

5VT

Default: PI10 Alternate: EXMC_D31

Remap: TLI_HSYNC, ENET_MII_RX_ER

PI11

13

I/O

5VT

Default: PI11

VSS

14

P

 

Default: VSS

VDD

15

P

 

Default: VDD

 

PF0

 

16

 

I/O

 

5VT

Default: PF0

Alternate: EXMC_A0 Remap: I2C1_SDA

PF1

17

I/O

5VT

Default: PF1

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: EXMC_A1

Remap: I2C1_SCL

 

PF2

 

18

 

I/O

 

5VT

Default: PF2 Alternate: EXMC_A2

Remap: I2C1_SMBA

 

PF3

 

19

 

I/O

 

5VT

Default: PF3

Alternate: EXMC_A3, ADC2_IN9

 

PF4

 

20

 

I/O

 

5VT

Default: PF4

Alternate: EXMC_A4, ADC2_IN14

 

PF5

 

21

 

I/O

 

5VT

Default: PF5

Alternate: EXMC_A5, ADC2_IN15

VSS_5

22

P

 

Default: VSS_5

VDD_5

23

P

 

Default: VDD_5

 

PF6

 

24

 

I/O

 

Default: PF6

Alternate: ADC2_IN4, EXMC_NIORD Remap: TIMER9_CH0, UART6_RX

 

PF7

 

25

 

I/O

 

Default: PF7

Alternate: ADC2_IN5, EXMC_NREG Remap: TIMER10_CH0, UART6_TX

 

PF8

 

26

 

I/O

 

Default: PF8

Alternate: ADC2_IN6, EXMC_NIOWR Remap: TIMER12_CH0

 

PF9

 

27

 

I/O

 

Default: PF9

Alternate: ADC2_IN7, EXMC_CD Remap: TIMER13_CH0

 

PF10

 

28

 

I/O

 

Default: PF10

Alternate: ADC2_IN8, EXMC_INTR Remap: DCI_D11, TLI_DE

 

OSCIN

 

29

 

I

 

Default: OSCIN

Remap: PD0, PH0

OSCO

UT

 

30

 

O

 

Default: OSCOUT Remap: PD1, PH1

NRST

31

I/O

 

Default: NRST

 

PC0

 

32

 

I/O

 

Default: PC0

Alternate: ADC012_IN10 Remap: EXMC_SDNWE

 

PC1

 

33

 

I/O

 

Default: PC1

Alternate: ADC012_IN11, ENET_MDC

 

PC2

 

34

 

I/O

 

Default: PC2

Alternate: ADC012_IN12, ENET_MII_TXD2 Remap: EXMC_SDNE0, SPI1_MISO

 

PC3

 

35

 

I/O

 

Default: PC3

Alternate: ADC012_IN13, ENET_MII_TX_CLK Remap: EXMC_SDCKE0, SPI1_MOSI, I2S1_SD

VSSA

36

P

 

Default: VSSA

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VREF-

37

P

 

Default: VREF-

VREF+

38

P

 

Default: VREF+

VDDA

39

P

 

Default: VDDA

 

PA0- WKUP

 

 

40

 

 

I/O

 

Default: PA0

Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, ENET_MII_CRS

Remap: UART3_TX

 

 

PA1

 

 

41

 

 

I/O

 

Default: PA1

Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1,ENET_MII_RX_CLK, ENET_RMII_REF_CLK

Remap: UART3_RX

 

PA2

 

42

 

I/O

 

Default: PA2

Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, ENET_MDIO, SPI0_IO3

 

PH2

 

43

 

I/O

 

5VT

Default: PH2

Alternate: EXMC_SDCKE0 Remap: TLI_R0, ENET_MII_CRS

 

PH3

 

44

 

I/O

 

5VT

Default: PH3

Alternate: EXMC_SDNE0 Remap: TLI_R1, ENET_MII_COL

 

PH4

 

45

 

I/O

 

5VT

Default: PH4

Remap: I2C1_SCL, TLI_R0

 

PH5

 

46

 

I/O

 

5VT

Default: PH5

Alternate: EXMC_SDNWE Remap: I2C1_SDA

 

 

PA3

 

 

47

 

 

I/O

 

Default: PA3

Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, ENET_MII_COL, SPI0_IO4

Remap: TLI_B5

VSS_4

48

P

 

Default: VSS_4

VDD_4

49

P

 

Default: VDD_4

 

 

PA4

 

 

50

 

 

I/O

 

Default: PA4

Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4, DCI_HSYNC

Remap: SPI2_NSS, I2S2_WS, TLI_VSYNC

 

PA5

 

51

 

I/O

 

Default: PA5

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

Remap: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON

 

 

PA6

 

 

52

 

 

I/O

 

Default: PA6

Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN, TIMER12_CH0, DCI_PIXCLK Remap: TIMER0_BRKIN, TLI_G2

 

PA7

 

53

 

I/O

 

Default: PA7

Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON, TIMER13_CH0, ENET_MII_RX_DV,

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

ENET_RMII_CRS_DV

Remap: TIMER0_CH0_ON

 

PC4

 

54

 

I/O

 

Default: PC4

Alternate: ADC01_IN14, ENET_MII_RXD0. ENET_RMII_RXD0

 

PC5

 

55

 

I/O

 

Default: PC5

Alternate: ADC01_IN15, ENET_MII_RXD1, ENET_RMII_RXD1

 

 

PB0

 

 

56

 

 

I/O

 

Default: PB0

Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON, ENET_MII_RXD2

Remap: TIMER0_CH1_ON, TLI_R3

 

 

PB1

 

 

57

 

 

I/O

 

Default: PB1

Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON, ENET_MII_RXD3

Remap: TIMER0_CH2_ON, TLI_R6

PB2

58

I/O

5VT

Default: PB2, BOOT1

 

PF11

 

59

 

I/O

 

5VT

Default: PF11

Alternate: EXMC_NIOS16, DCI_D12, EXMC_SDNRAS

 

PF12

 

60

 

I/O

 

5VT

Default: PF12

Alternate: EXMC_A6

VSS_6

61

P

 

Default: VSS_6

VDD_6

62

P

 

Default: VDD_6

 

PF13

 

63

 

I/O

 

5VT

Default: PF13 Alternate: EXMC_A7

 

PF14

 

64

 

I/O

 

5VT

Default: PF14

Alternate: EXMC_A8

 

PF15

 

65

 

I/O

 

5VT

Default: PF15 Alternate: EXMC_A9

 

PG0

 

66

 

I/O

 

5VT

Default: PG0

Alternate: EXMC_A10

 

PG1

 

67

 

I/O

 

5VT

Default: PG1 Alternate: EXMC_A11

 

PE7

 

68

 

I/O

 

5VT

Default: PE7

Alternate: EXMC_D4, UART6_RX Remap: TIMER0_ETI

 

PE8

 

69

 

I/O

 

5VT

Default: PE8

Alternate: EXMC_D5, UART6_TX Remap: TIMER0_CH0_ON

 

PE9

 

70

 

I/O

 

5VT

Default: PE9 Alternate: EXMC_D6

Remap: TIMER0_CH0

VSS_7

71

P

 

Default: VSS_7

VDD_7

72

P

 

Default: VDD_7

 

PE10

 

73

 

I/O

 

5VT

Default: PE10 Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PE11

 

74

 

I/O

 

5VT

Default: PE11 Alternate: EXMC_D8

Remap: TIMER0_CH1, TLI_G3

 

PE12

 

75

 

I/O

 

5VT

Default: PE12 Alternate: EXMC_D9

Remap: TIMER0_CH2_ON, TLI_B4

 

PE13

 

76

 

I/O

 

5VT

Default: PE13 Alternate: EXMC_D10

Remap: TIMER0_CH2, TLI_DE

 

PE14

 

77

 

I/O

 

5VT

Default: PE14 Alternate: EXMC_D11

Remap: TIMER0_CH3, TLI_ PIXCLK

 

PE15

 

78

 

I/O

 

5VT

Default: PE15 Alternate: EXMC_D12

Remap: TIMER0_BRKIN, TLI_R7

 

PB10

 

79

 

I/O

 

5VT

Default: PB10

Alternate: I2C1_SCL, USART2_TX, ENET_MII_RX_ER Remap: TIMER1_CH2, TLI_G4, SPI1_SCK, I2S1_CK

 

 

PB11

 

 

80

 

 

I/O

 

 

5VT

Default: PB11

Alternate: I2C1_SDA, USART2_RX, ENET_MII_TX_EN, ENET_RMII_TX_EN

Remap: TIMER1_CH3, TLI_G5

VSS_1

81

P

 

Default: VSS_1

VDD_1

82

P

 

Default: VDD_1

 

PH6

 

83

 

I/O

 

5VT

Default: PH6

Alternate: EXMC_SDNE1

Remap: I2C1_SMBA, TIMER11_CH0, ENET_MII_RXD2, DCI_D8

 

PH7

 

84

 

I/O

 

5VT

Default: PH7

Alternate: EXMC_SDCKE1

Remap: I2C2_SCL, ENET_MII_RXD3, DCI_D9

 

PH8

 

85

 

I/O

 

5VT

Default: PH8 Alternate: EXMC_D16

Remap: TLI_R2, I2C2_SDA, DCI_HSYNC

 

PH9

 

86

 

I/O

 

5VT

Default: PH9 Alternate: EXMC_D17

Remap: TLI_R3, I2C2_SMBA, TIMER11_CH1, DCI_D0

 

PH10

 

87

 

I/O

 

5VT

Default: PH10 Alternate: EXMC_D18

Remap: TLI_R4, TIMER4_CH0, DCI_D1

 

PH11

 

88

 

I/O

 

5VT

Default: PH11 Alternate: EXMC_D19

Remap: TLI_R5, TIMER4_CH1, DCI_D2

 

PH12

 

89

 

I/O

 

5VT

Default: PH12 Alternate: EXMC_D20

Remap: TLI_R6, TIMER4_CH2, DCI_D3

VSS

90

P

 

Default: VSS

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

VDD

91

P

 

Default: VDD

 

PB12

 

92

 

I/O

 

5VT

Default: PB12

Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS, CAN1_RX, ENET_MII_TXD0, ENET_RMII_TXD0

 

PB13

 

93

 

I/O

 

5VT

Default: PB13

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX , ENET_MII_TXD1, ENET_RMII_TXD1

 

PB14

 

94

 

I/O

 

5VT

Default: PB14

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0

 

PB15

 

95

 

I/O

 

5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1

 

PD8

 

96

 

I/O

 

5VT

Default: PD8 Alternate: EXMC_D13

Remap: USART2_TX, ENET_MII_RX_DV, ENET_RMII_CRS_DV

 

PD9

 

97

 

I/O

 

5VT

Default: PD9 Alternate: EXMC_D14

Remap: USART2_RX, ENET_MII_RXD0, ENET_RMII_RXD0

 

 

PD10

 

 

98

 

 

I/O

 

 

5VT

Default: PD10 Alternate: EXMC_D15

Remap: USART2_CK, ENET_MII_RXD1, ENET_RMII_RXD1,

TLI_B3

 

PD11

 

99

 

I/O

 

5VT

Default: PD11 Alternate: EXMC_A16

Remap: USART2_CTS, ENET_MII_RXD2

 

PD12

 

100

 

I/O

 

5VT

Default: PD12 Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS

 

PD13

 

101

 

I/O

 

5VT

Default: PD13 Alternate: EXMC_A18

Remap: TIMER3_CH1

VSS_8

102

P

 

Default: VSS_8

VDD_8

103

P

 

Default: VDD_8

 

PD14

 

104

 

I/O

 

5VT

Default: PD14

Alternate: EXMC_D0 Remap: TIMER3_CH2

 

PD15

 

105

 

I/O

 

5VT

Default: PD15

Alternate: EXMC_D1 Remap: TIMER3_CH3

 

PG2

 

106

 

I/O

 

5VT

Default: PG2

Alternate: EXMC_A12

 

PG3

 

107

 

I/O

 

5VT

Default: PG3 Alternate: EXMC_A13

 

PG4

 

108

 

I/O

 

5VT

Default: PG4

Alternate: EXMC_A14, EXMC_BA0

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PG5

 

109

 

I/O

 

5VT

Default: PG5

Alternate: EXMC_A15, EXMC_BA1

 

PG6

 

110

 

I/O

 

5VT

Default: PG6 Alternate: EXMC_INT1

Remap: DCI_D12, TLI_R7

 

PG7

 

111

 

I/O

 

5VT

Default: PG7

Alternate: EXMC_INT2, DCI_D13 Remap: USART5_CK, TLI_ PIXCLK

 

PG8

 

112

 

I/O

 

5VT

Default: PG8

Alternate: EXMC_SDCLK, USART5_RTS Remap: ENET_PPS_OUT

VSS_9

113

P

 

Default: VSS_9

VDD_9

114

P

 

Default: VDD_9

 

PC6

 

115

 

I/O

 

5VT

Default: PC6

Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6, USART5_TX Remap: TIMER2_CH0, DCI_D0, TLI_HSYNC

 

PC7

 

116

 

I/O

 

5VT

Default: PC7

Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7, USART5_RX Remap: TIMER2_CH1, DCI_D1, TLI_G6

 

PC8

 

117

 

I/O

 

5VT

Default: PC8

Alternate: TIMER7_CH2, SDIO_D0, DCI_D2, USART5_CK

Remap: TIMER2_CH2

 

PC9

 

118

 

I/O

 

5VT

Default: PC9

Alternate: TIMER7_CH3, SDIO_D1, DCI_D3, CK_OUT1 Remap: TIMER2_CH3, I2C2_SDA

 

 

PA8

 

 

119

 

 

I/O

 

 

5VT

Default: PA8

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF

Remap: TLI_R6, I2C2_SCL

 

PA9

 

120

 

I/O

 

5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS, DCI_D0

Remap: I2C2_SMBAI

 

PA10

 

121

 

I/O

 

5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, DCI_D1

 

PA11

 

122

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

Remap: TLI_R4

 

PA12

 

123

 

I/O

 

5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

Remap: TLI_R5

 

PA13

 

124

 

I/O

 

5VT

Default: JTMS, SWDIO

Remap: PA13

NC

125

 

 

-

VSS_2

126

P

 

Default: VSS_2

VDD_2

127

P

 

Default: VDD_2

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PH13

 

128

 

I/O

 

5VT

Default: PH13 Alternate: EXMC_D21

Remap: TLI_G2, TIMER7_CH0_ON, CAN0_TX

 

PH14

 

129

 

I/O

 

5VT

Default: PH14 Alternate: EXMC_D22

Remap: TLI_G3, TIMER7_CH1_ON, DCI_D4

 

PH15

 

130

 

I/O

 

5VT

Default: PH15 Alternate: EXMC_D23

Remap: TLI_G4, TIMER7_CH2_ON, DCI_D11

 

PI0

 

131

 

I/O

 

5VT

Default: PI0

Alternate: EXMC_D24

Remap: TLI_G5, TIMER4_CH3, SPI1_NSS, I2S1_WS, DCI_D13

 

PI1

 

132

 

I/O

 

5VT

Default: PI1

Alternate: EXMC_D25

Remap: TLI_G6, SPI1_SCK, I2S1_CK, DCI_D8

 

PI2

 

133

 

I/O

 

5VT

Default: PI2

Alternate: EXMC_D26

Remap: TLI_G7, TIMER7_CH3, SPI1_MISO, DCI_D9

 

PI3

 

134

 

I/O

 

5VT

Default: PI3

Alternate: EXMC_D27

Remap: TIMER7_ETI, SPI1_MOSI, I2S1_SD, TLI_R1, DCI_D10

VSS

135

P

 

Default: VSS

VDD

136

P

 

Default: VDD

 

PA14

 

137

 

I/O

 

5VT

Default: JTCK, SWCLK Remap: PA14

 

PA15

 

138

 

I/O

 

5VT

Default: JTDI

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS

 

PC10

 

139

 

I/O

 

5VT

Default: PC10

Alternate: UART3_TX, SDIO_D2, DCI_D8

Remap: USART2_TX, SPI2_SCK, I2S2_CK, TLI_R2

 

PC11

 

140

 

I/O

 

5VT

Default: PC11

Alternate: UART3_RX, SDIO_D3, DCI_D4 Remap: USART2_RX, SPI2_MISO

 

PC12

 

141

 

I/O

 

5VT

Default: PC12

Alternate: UART4_TX, SDIO_CK, DCI_D9 Remap: USART2_CK, SPI2_MOSI, I2S2_SD

 

PD0

 

142

 

I/O

 

5VT

Default: PD0 Alternate: EXMC_D2

Remap: CAN0_RX, OSCIN

 

PD1

 

143

 

I/O

 

5VT

Default: PD1 Alternate: EXMC_D3

Remap: CAN0_TX, OSCOUT

 

PD2

 

144

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11

PD3

145

I/O

5VT

Default: PD3

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: EXMC_CLK

Remap: USART1_CTS, DCI_D5, TLI_G7, SPI1_SCK, I2S1_CK

 

PD4

 

146

 

I/O

 

5VT

Default: PD4 Alternate: EXMC_NOE

Remap: USART1_RTS

 

PD5

 

147

 

I/O

 

5VT

Default: PD5

Alternate: EXMC_NWE Remap: USART1_TX

VSS_10

148

P

 

Default: VSS_10

VDD_10

149

P

 

Default: VDD_10

 

PD6

 

150

 

I/O

 

5VT

Default: PD6

Alternate: EXMC_NWAIT

Remap: USART1_RX, DCI_D10, TLI_B2, SPI2_MOSI, I2S2_SD

 

PD7

 

151

 

I/O

 

5VT

Default: PD7

Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK

 

PG9

 

152

 

I/O

 

5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2 Remap: DCI_VSYNC, USART5_RX

 

PG10

 

153

 

I/O

 

5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2 Remap: DCI_D2, TLI_G3, TLI_B2

 

PG11

 

154

 

I/O

 

5VT

Default: PG11

Alternate: EXMC_NCE3_1

Remap: DCI_D3, TLI_B3, ENET_MII_TX_EN, ENET_RMII_TX_EN

 

PG12

 

155

 

I/O

 

5VT

Default: PG12 Alternate: EXMC_NE3

Remap: USART5_RTS, TLI_B4, TLI_B1

 

PG13

 

156

 

I/O

 

5VT

Default: PG13 Alternate: EXMC_A24

Remap: USART5_CTS, ENET_MII_TXD0, ENET_RMII_TXD0

 

PG14

 

157

 

I/O

 

5VT

Default: PG14 Alternate: EXMC_A25

Remap: USART5_TX, ENET_MII_TXD1, ENET_RMII_TXD1

VSS_11

158

P

 

Default: VSS_10

VDD_11

159

P

 

Default: VDD_10

 

PG15

 

160

 

I/O

 

5VT

Default: PG15

Alternate: EXMC_SDNCAS, USART5_CTS Remap: DCI_D13

 

PB3

 

161

 

I/O

 

5VT

Default: JTDO Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK

 

PB4

 

162

 

I/O

 

5VT

Default: JNTRST Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

 

Pin

Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

PB5

 

 

163

 

 

I/O

 

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD, ENET_PPS_OUT, DCI_D10

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX, EXMC_SDCKE1

 

PB6

 

164

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, TIMER3_CH0, DCI_D5

Remap: USART0_TX, CAN1_TX, EXMC_SDNE1, SPI0_IO3

 

PB7

 

165

 

I/O

 

5VT

Default: PB7

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NL, DCI_VSYNC Remap: USART0_RX, SPI0_IO4

BOOT0

166

I

 

Default: BOOT0

 

 

PB8

 

 

167

 

 

I/O

 

 

5VT

Default: PB8

Alternate: TIMER3_CH2, TIMER9_CH0, ENET_MII_TXD3, SDIO_D4, DCI_D6

Remap: I2C0_SCL, CAN0_RX, TLI_B6

 

PB9

 

168

 

I/O

 

5VT

Default: PB9

Alternate: TIMER3_CH3, TIMER10_CH0, SDIO_D5, DCI_D7 Remap: I2C0_SDA, CAN0_TX, TLI_B7, SPI1_NSS, I2S1_WS

 

PE0

 

169

 

I/O

 

5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0, UART7_RX

Remap: DCI_D2

 

PE1

 

170

 

I/O

 

5VT

Default: PE1

Alternate: EXMC_NBL1, UART7_TX Remap: DCI_D3

VSS_3

171

P

 

Default: VSS_3

VDD_3

172

P

 

Default: VDD_3

 

PI4

 

173

 

I/O

 

5VT

Default: PI4

Alternate: EXMC_NBL2

Remap: TLI_B4, TIMER7_BRKIN, DCI_D5

 

PI5

 

174

 

I/O

 

5VT

Default: PI5

Alternate: EXMC_NBL3

Remap: TLI_B5, TIMER7_CH0, DCI_VSYNC

 

PI6

 

175

 

I/O

 

5VT

Default: PI6

Alternate: EXMC_D28

Remap: TLI_B6, TIMER7_CH1, DCI_D6

 

PI7

 

176

 

I/O

 

5VT

Default: PI7

Alternate: EXMC_D29

Remap: TLI_B7, TIMER7_CH2, DCI_D7

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
 

ARM® Cortex®-M3 core

The Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M3 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 3072 Kbytes of flash memory, including code flash and data flash
Up to 256 Kbytes of SRAM

The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner flash at most, which includes code flash and data flash is available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. Up to 256 Kbytes of inner SRAM is composed of SRAM0, SRAM1, and SRAM2 that can be accessed at same time. Table 2-2. GD32F207xx memory map shows the memory map of the GD32F207xx series of devices, including flash, SRAM, peripheral, and other pre-defined regions.

Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB/APB2/APB1 domains is 120/120/60 MHz. See Figure 2-6. GD32F207xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6) and USB (PA9, PA10, PA11 and PA12). It also can be used to transfer and update the flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of flash memory is selected. It also supports to boot from bank 1 of flash memory by setting a bit in option bytes.

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, the Ethernet wakeup and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC engine with up to 2 MSPS conversion rate
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

Up to three 12-bit 2 MSPS multi-channel ADC are integrated in the device. It is a total of up to 16 multiplexed external channels with 2 internal channels for temperature sensor and voltage reference measurement. The conversion range is between 2.6 V < VDDA < 3.6 V. An on-chip 16-bit hardware oversample scheme improves performances while off-loading the related computational burden from the MCU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally

connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

Digital to analog converter (DAC)

12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

14 channels DMA controller and each channel are configurable (7 for DMA0 and 7 for DMA1)
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO, DCI, CAU and HAU
The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 140 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 140 general purpose I/O pins (GPIO) in GD32F207xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH15 and PI0 ~ PI11 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are

shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

Timers and PWM generation

Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)

The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a 16-bit general timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer, known as TIMER1 ~ TIMER4, TIMER8 ~ TIMER13 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The general timer is based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. TIMER1 ~ TIMER4 and TIMER8/TIMER11 also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F207xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, it is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter.

The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC) and backup registers

32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
84 bytes backup registers for data protection

The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
The backup registers are located in the backup domain that remains powered-on by VBAT even if VDD power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from standby mode or system reset do not affect these registers.
In addition, the backup registers can be used to implement the tamper detection, RTC calibration function and waveform detection.

Inter-integrated circuit (I2C)

Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking

for I2C data.


Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad wire configuration available in master mode (only in SPI0)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI0.

Universal    synchronous/asynchronous    receiver    transmitter (USART/UART)
Up to four USARTs and four UARTs with operating frequency up to 7.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6,
UART7) are used to transmit data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI1 and SPI2
Support either master or slave mode audio
Sampling frequencies from 8 KHz up to 192 KHz are supported.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F207xx contain an I2S-bus interface that can be operated with 16/32-bit resolution in master or slave mode, pin multiplexed with SPI1 and

SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.

Universal serial bus full-speed interface (USBFS)

One USB device/host full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.

Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

Ethernet (ENET)

IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 16 with 25 MHz output and RMII up to 7 with 50 MHz output. The function of 32-bit CRC checking is also available.

External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and PC card, SDRAM with up to 32-bit data bus
Provide ECC calculating hardware module for NAND Flash memory block
Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits Column Address, 2-bits internal banks address
SDRAM Memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)
External memory controller (EXMC) is an abbreviation of external memory controller. It is divided into several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and PC card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.
The EXMC of GD32F207xx in LQFP144 package above also supports synchronous dynamic random access memory (SDRAM). It translates AHB transactions into the appropriate SDRAM protocol, and meanwhile, makes sure the access time requirements of the external SDRAM devices are satisfied.

Secure digital input and output card interface (SDIO)

Support SD2.0/SDIO2.0/MMC4.2 host interface

The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.

TFT LCD interface (TLI)

24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)
Supports up to SVGA (800x600) resolution

The TFT LCD interface provides a parallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display. Two separate layers are supported in TLI, as well as layer window and blending function.

Digital camera interface (DCI)

Digital video/picture capture
8/10/12/14 data width supported
High transfer efficiency with DMA interface
Video/picture crop supported
Various pixel formats supported including JPEG/YCrCb/RGB
Hard/embedded synchronous signals supported

DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation.

Cryptographic acceleration Unit (CAU)

Supports DES, 3DES or AES algorithm
DES/3DES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode
3DES supports 64bits-key, 128bits-key or 192bits-key
AES supports 128bits-key, 192bits-key or 256 bits-key
AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode or Counter mode (CTR) mode
Support DMA mode for input data flow

The Cryptographic Acceleration Unit supports acceleration of DES, 3DES or AES (128, 192, or 256) algorithms. The DES/3DES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode. The AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode or Counter mode (CTR) mode.

Hash acceleration unit (HAU)

Supports SHA-1, SHA-224 and SHA-256 algorithms, compliant with FIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2)
Supports MD5 compliant with IETF RFC 1321 (Internet Engineering Task Force Request For Comments number 1321)
Supports HMAC (keyed-hash message authentication code) algorithm
Automatic swapping to comply with the big-endian or little-endian for MD5, SHA-1, SHA- 224 and SHA-256 algorithms
Automatic padding to fit module 512
Support DMA mode for input data flow

The HAU supports acceleration of SHA-1, SHA-224, SHA-256, MD5 algorithm and the HMAC (keyed-hash message authentication code) algorithm, which calling the SHA-1, SHA-224, SHA-256 or MD5 hash function to calculate key, message, digest three times.

True Random number generator (TRNG)

About 40 period PLL clock consumed between two consecutive random numbers
Disable TRNG module will reduce the chip power consumption
32-bit random value seed is generated from analog noise

The true random number generator (TRNG) module can generate a 32-bit value using continuous analog noise.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP176 (GD32F207Ix), LQFP144 (GD32F207Zx), LQFP100 (GD32F207Vx), LQFP64 (GD32F207Rx)
Operation temperature range: -40°C to +85°C (industrial level)

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uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗,指纹门锁并不是什么新鲜事,我相信每个人都很熟悉。随着近年来智能家居的逐步普及,指纹门锁也进入了成千上万的家庭。今天的功耗雷达模块指纹门锁不仅消除了繁琐的钥匙,而且还提供了各种智能功能,uA级别智能门锁低功耗雷达模块用在智能门锁上,可以实现门锁的智能感应屏幕,使电池寿命延长3-5倍,如与其他智能家居连接,成为智能场景的开关。所以今天的指纹门锁更被称为智能门锁。 今天,让我们来谈谈功耗雷达模块智能门锁的安全性。希望能让更多想知道智能门锁的朋友认识下。 指纹识别是智能门锁的核心 指纹识别技术在我们的智能手机上随处可见。从以前的实体指纹识别到屏幕下的指纹识别,可以说指纹识别技术已经相当成熟。指纹识别可以说是整个uA级低功耗雷达模块智能门锁的核心。 目前主要有三种常见的指纹识别方法,即光学指纹识别、半导体指纹识别和超声指纹识别。 光学指纹识别 让我们先谈谈光学指纹识别的原理实际上是光的反射。我们都知道指纹本身是不均匀的。当光照射到我们的指纹上时,它会反射,光接收器可以通过接收反射的光来绘制我们的指纹。就像激光雷达测绘一样。 光学指纹识别通常出现在打卡机上,手机上的屏幕指纹识别技术也使用光学指纹识别。今天的光学指纹识别已经达到了非常快的识别速度。 然而,光学指纹识别有一个缺点,即硬件上的活体识别无法实现,容易被指模破解。通常,活体识别是通过软件算法进行的。如果算法处理不当,很容易翻车。 此外,光学指纹识别也容易受到液体的影响,湿手解锁的成功率也会下降。 超声指纹识别 超声指纹识别也被称为射频指纹识别,其原理与光学类型相似,但超声波使用声波反射,实际上是声纳的缩小版本。因为使用声波,不要担心水折射会降低识别率,所以超声指纹识别可以湿手解锁。然而,超声指纹识别在防破解方面与光学类型一样,不能实现硬件,可以被指模破解,活体识别仍然依赖于算法。 半导体指纹识别 半导体指纹识别主要采用电容、电场(即我们所说的电感)、温度和压力原理来实现指纹图像的收集。当用户将手指放在前面时,皮肤形成电容阵列的极板,电容阵列的背面是绝缘极板。由于不同区域指纹的脊柱与谷物之间的距离也不同,因此每个单元的电容量随之变化,从而获得指纹图像。半导体指纹识别具有价格低、体积小、识别率高的优点,因此大多数uA级低功耗雷达模块智能门锁都采用了这种方案。半导体指纹识别的另一个功能是活体识别。传统的硅胶指模无法破解。 当然,这并不意味着半导体可以百分识别活体。所谓的半导体指纹识别活体检测不使用指纹活体体征。本质上,它取决于皮肤的材料特性,这意味着虽然传统的硅胶指模无法破解。 一般来说,无论哪种指纹识别,都有可能被破解,只是说破解的水平。然而,今天的指纹识别,无论是硬件生活识别还是算法生活识别,都相对成熟,很难破解。毕竟,都可以通过支付级别的认证,大大保证安全。 目前,市场上大多数智能门锁仍将保留钥匙孔。除了指纹解锁外,用户还可以用传统钥匙开门。留下钥匙孔的主要目的是在指纹识别故障或智能门锁耗尽时仍有开门的方法。但由于有钥匙孔,它表明它可以通过技术手段解锁。 目前市场上的锁等级可分为A、B、C三个等级,这三个等级主要是通过防暴开锁和防技术开锁的程度来区分的。A级锁要求技术解锁时间不少于1分钟,B级锁要求不少于5分钟。即使是高级别的C级锁也只要求技术解锁时间不少于10分钟。 也就是说,现在市场上大多数门锁,无论是什么级别,在专业的解锁大师面前都糊,只不过是时间长短。 安全是重要的,是否安全增加了人们对uA级别低功耗雷达模块智能门锁安全的担忧。事实上,现在到处都是摄像头,强大的人脸识别,以及移动支付的出现,使家庭现金减少,所有这些都使得入室盗窃的成本急剧上升,近年来各省市的入室盗窃几乎呈悬崖状下降。 换句话说,无论锁有多安全,无论锁有多难打开,都可能比在门口安装摄像头更具威慑力。 因此,担心uA级别低功耗雷达模块智能门锁是否不安全可能意义不大。毕竟,家里的防盗锁可能不安全。我们应该更加关注门锁能给我们带来多少便利。 我们要考虑的是智能门锁的兼容性和通用性。毕竟,智能门锁近年来才流行起来。大多数人在后期将普通机械门锁升级为智能门锁。因此,智能门锁能否与原门兼容是非常重要的。如果不兼容,发现无法安装是一件非常麻烦的事情。 uA级别低功耗雷达模块智能门锁主要是为了避免带钥匙的麻烦。因此,智能门锁的便利性尤为重要。便利性主要体现在指纹的识别率上。手指受伤导致指纹磨损或老年人指纹较浅。智能门锁能否识别是非常重要的。 当然,如果指纹真的失效,是否有其他解锁方案,如密码解锁或NFC解锁。还需要注意密码解锁是否有虚假密码等防窥镜措施。 当然,智能门锁的耐久性也是一个需要特别注意的地方。uA级别低功耗雷达模块智能门锁主要依靠内部电池供电,这就要求智能门锁的耐久性尽可能好,否则经常充电或更换电池会非常麻烦。
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14
2022-01

微波雷达传感器雷达感应浴室镜上的应用

发布时间: : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用,如今,家用电器的智能化已成为一种常态,越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入,今天就来说说这个话题。 什么是智能浴室镜?智慧型浴室镜,顾名思义,就是卫浴镜子智能化升级,入门级产品基本具备了彩灯和镜面触摸功能,更高档次的产品安装有微波雷达传感器智能感应,当感应到有人接近到一定距离即可开启亮灯或者亮屏操作,也可三色无极调,智能除雾,语音交互,日程安排备忘,甚至在镜子上看电视,听音乐,气象预报,问题查询,智能控制,健康管理等。 智能化雷达感应浴室镜与普通镜的区别,为什么要选TA?,就功能而言,普通浴镜价格用它没有什么压力!而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言,普通浴镜功能单一,而微波雷达传感器智能浴室镜功能创新:镜子灯光色温和亮度可以自由调节,镜面还可以湿手触控,智能除雾,既环保又健康! 尽管智能浴镜比较新颖,但功能丰富,体验感更好,特别是入门级的智能浴镜,具有基础智能化功能,真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么? ①确定智能浴室镜的安装位置,因为是安装时在墙壁上打孔,一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时,根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后,在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度,一般智能浴镜的标准安装高度约85cm(从地砖到镜子底),具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍,可用酒精或30%清洁稀释液擦洗,平时可用干毛巾养护,注意多通风。
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07
2022-02

冰箱屏幕唤醒微波雷达传感器屏幕唤醒性能强悍智能感应

发布时间: : 2022-02--07
冰箱屏幕唤醒微波雷达传感器屏幕唤醒性能强悍智能感应,随着年轻一代消费观念的转变,冰箱作为厨房和客厅的核心家用电器之一,也升级为健康、智能、高端的形象。在新产品发布会上,推出了大屏幕的冰箱,不仅屏幕优秀,而且微波雷达传感器屏幕唤醒性能强大。 大屏智能互联,听歌看剧购物新体验 冰箱植入冰箱屏幕唤醒微波雷达传感器触摸屏,重新定义了冰箱的核心价值。除了冰箱的保鲜功能外,该显示屏还集控制中心、娱乐中心和购物中心于一体,让您在无聊的烹饪过程中不会落后于听歌、看剧和购物。新的烹饪体验是前所未有的。 不仅如此,21.5英寸的屏幕也是整个房子智能互联的互动入口。未来的家将是一个充满屏幕的家。冰箱可以通过微波雷达传感器屏幕与家庭智能产品连接。烹饪时,你可以通过冰箱观看洗衣机的工作,当你不能腾出手来照顾孩子时,你可以通过冰箱屏幕连接家庭摄像头,看到孩子的情况。冰箱的推出标志着屏幕上的未来之家正在迅速到来。 管理RFID食材,建立健康的家庭生活 据报道,5G冰箱配备了RFID食品材料管理模块,用户将自动记录和储存食品,无需操作。此外,冰箱还可以追溯食品来源,监控食品材料从诞生到用户的整个过程,以确保食品安全;当食品即将过期时,冰箱会自动提醒用户提供健康的饮食和生活。 风冷无霜,清新无痕 冰箱的出现是人类延长食品保存期的一项伟大发明。一个好的冰箱必须有很强的保存能力。5g冰箱采用双360度循环供气系统。智能补水功能使食品原料享受全方位保鲜,紧紧锁住水分和营养,防止食品原料越来越干燥。此外,该送风系统可将其送到冰箱的每个角落,消除每个储藏空间的温差,减少手工除霜的麻烦,使食品不再粘连。 进口电诱导保鲜技术,创新黑科技加持 针对传统冰箱保存日期不够长的痛点,5g互联网冰箱采用日本进口电诱导保存技术,不仅可以实现水果储存冰箱2周以上不腐烂发霉,还可以使蔬菜储存25天不发黄、不起皱。在-1℃~-5℃下,配料不易冻结,储存时间较长。冷冻食品解冻后无血,营养大化。此外,微波雷达传感器5g冰箱还支持-7℃~-24℃的温度调节,以满足不同配料的储存要求。 180°矢量变频,省电时更安静 一台好的压缩机对冰箱至关重要。冰箱配备了变频压缩机。180°矢量变频技术可根据冷藏室和冷冻室的需要有效提供冷却,达到食品原料的保鲜效果。180°矢量变频技术不仅大大降低了功耗,而且以非常低的分贝操作机器。保鲜效果和节能安静的技术冰箱可以在许多智能冰箱中占有一席之地,仅仅通过这种搭配就吸引了许多消费者的青睐。 配备天然草本滤芯,不再担心串味 各种成分一起储存在冰箱中,难以避免串味。此外,冰箱内容易滋生细菌,冰箱总是有异味。针对这一问题,冰箱创新配置了天然草本杀菌除臭滤芯。该滤芯提取了多种天然草本活性因子,可有效杀菌99.9%,抑制冰箱异味,保持食材新鲜。不仅如此,这个草本滤芯可以更快、更方便、更无忧地拆卸。家里有冰箱,开始健康保鲜的生活。 目前,冰箱屏幕唤醒微波雷达传感器正在继续推动家庭物联网的快速普及,相信在不久的将来,智能家电将成为互动终端。
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29
2022-09

蓝牙Beacon 2.4G wifi无线模组特点门铃场景中的应用

发布时间: : 2022-09--29
蓝牙Beacon 2.4G wifi无线模组特点门铃场景中的应用,低功耗蓝牙Beacon技术让很多商家产生了兴趣,通过Beacon技术向兼容的移动设备发送信号,可以推广商品以及活动信息等吸引消费者。Beacon 2.4G wifi无线模组通过蓝牙的广播和扫描协议进行通讯,下面介绍Beacon 2.4G无线模块的特点,以及应用在哪些项目中。 Beacon 2.4G wifi无线模组的特点 1.可与手机相连的2.4G模块 2.可与BLE设备相互通讯 3.支持开发Beacon、iBeacon协议 4.通过蓝牙的广播和扫描协议进行通讯 蓝牙Beacon 2.4G wifi无线模组一般在哪些项目中使用 一、商场、展柜消息推送 当消费者在商场中靠近某个安装有Beacon设备的展柜一定范围时,如果消费者的手机与Beacon设备相兼容,那么就可以推送消息给消费者,比如通知消费者有哪些新品,哪些产品正在打折等等,以这样的方式刺激消费访问商家。 二、室内定位 将beacon设备放置在某些场所,可以了解到用户位置的变化。 将距离简单分为三级。苹果在iOS中并不仔细推断距离,将距离分为贴近贴近(Immediate)、1m以内(Near)、1m以上(Far)三种距离状态。 距离在1m以内时,RSSI值基本上成比例减少,而距离在1m以上时,由于反射波的影响等,RSSI不减少而是上下波动。也就是说,相距1m以上时无法推断距离,因此就简单判定为Far。 三、数据传送(温湿度传送) 可以将采集的温度通过Beacon广播发给手机。 以上就是Beacon 2.4G wifi无线模组的特点,这款产品常应用在无线鼠标、无线健康运动产品、商品信息推送、无线遥感、报警安保系统、无线测距系统等行业中。 2.4G wifi无线模组在门铃场景中的应用,门铃是现代生活常见的一个生活家具,它可以用于城市中的高楼大厦、高层住宅、甚至我们的民间楼房都可以使用到门铃。门铃从只有客人叫门的作用,发展到现在门户信息之间的传递、大门控制、出现紧急情况向门卫报警等等功能,都预示着门铃不断向着智能发现发展。 传统的门铃安装方式都是有线安装,发射器和接收器都是依靠电线连接的,发射器发出的信号是通过电线传输至接收器,所以有线门铃大优势就是它的信号比较稳定,也不会发生误响等情况,但是由于布线比较麻烦,很可能需要凿墙等,在如今遍地都是高楼大厦的城市中,显得很是麻烦,因而近几年逐渐淡出市场。 有线门铃的淡出,也意味着无线门铃的兴起,现在一栋栋的高楼大厦不断的建设当中,无线门铃的应用市场也是相当的巨大。那么大家知道无线门铃的原理是什么吗? 无线门铃关键的一点,就是如何取代有线方式的信号传输问题?现在市面上的无线门铃是在发射器和接收器中各安装一个2.4Gwifi无线模组来代替线缆的信号传输,无线模块可以很有效的解决凿墙布线的问题,还可以节省不少的成本,成为当下主流的无线门铃选择方案。 但是市面有各式各样,不同类型的无线模块,那么无线门铃一般都是选择那种来使用呢?大家都知道门铃的价格一直都是非常的便宜,所以2.4Gwifi无线模组就成为了无线门铃的首选,有人会问了,为什么不是选择同样便宜的蓝牙模块呢?那是因为蓝牙模块的传输距离比较短,且蓝牙模块之间只能点对点使用,不符合实际的应用场景。 2.4G wifi无线模组是可以进行二次开发的,通过单片机,写入一段程序,控制无线模块进行工作。无线模块就设有一个数据端口方便用户直接连接单片机,目的就是为了用户研发和生产的时候更加方便快捷。
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28
2022-09

远距离WiFi模块抗干扰能力的提高

发布时间: : 2022-09--28
远距离WiFi模块抗干扰能力的提高,远距离WiFi模块的抗干扰能力是无法进行具体数值化,所以它一般不会做为常规参数放在无线模块的规格书里,那么无线模块的抗干扰能力到底重不重要呢?答案是:非常重要。在同一发射功率和接收灵敏度的条件下,那么抗干扰能力更强的无线模块可以传输的距离会更远。 为什么提高抗干扰能力会提高通讯距离呢?远距离WiFi模块在收发通讯时,干扰源是无处不在的(磁场、金属、墙壁等),信号在空中发射时就会受到干扰源的不断干扰,导致信号强度会不断衰弱,到信号衰减到一定程度时,接收机就会接收不到发射过来的信号,从而导致通讯距离的缩短。 干扰源可以完全规避吗?哪怕是有线的通讯方式也会存在干扰的情况,所以我们没有办法去完全规避掉干扰源,所以好的办法就是提高无线模块的抗干扰能力,那么提高远距离WiFi模块抗干扰能力有哪些呢? 1. 远离干扰源 尽量避免在干扰源多的地方使用无线模块(避开干扰源是有效且直接的办法)。 2. 带宽 在无线通讯领域中,带宽越窄,代表着抗干扰能力就越好,所以适当的修改无线模块的带宽,可以很好提升无线模块在通讯时的抗干扰能力。 3. 降低传输速率 传输速率越快,会导致信号强度衰减的越快,适当的降低传输速率可以增强信号强度,从而提升无线模块的抗干扰能力。 4. 定向天线 我们发射远距离WiFi模块可以采用高增益的定向天线,定向天线它可以指定某一个或者多个方向发射及接收电磁波特别强,而在其他的方向上发射及接收电磁波则为零或极小的一种天线。定向天线的用处就是可以增加信号的强度,从而提升无线模块的抗干扰能力。 5. 屏蔽罩 屏蔽罩是无线模块提高的抗干扰能力好一个办法,屏蔽罩的可以屏蔽掉一定外界干扰源对芯片的影响,同时也能防止无线模块工作时对外界产生干扰和辐射。 6. 滤波器 滤波器是根据频率来区分的,例如:433MHz就只能使用对应频率的滤波器,它主要的功能是过滤掉其他不属于433MHz的频率,防止受到其他频段的干扰,从而达到抗干扰能力的效果。 今天的如何提高远距离WiFi模块的抗干扰能力就到这里结束了,如果您还有更好的提高抗干扰能力的方法也可以分享给我们,欢迎大家随时联系我司。 远距离WiFi模块为什么要加屏蔽罩外壳?作为现代化物联网中重要的一个环节,在市场上的可以说是非常受欢迎的。远距离WiFi模块的种类也可以说是五花八门,各种功能的无线模块在市面上都逐一崭露头角。但是大家有注意到大部分无线模块都会带有一个金属外壳吗?又知道这个金属外壳对无线模块能起到什么作用吗? 远距离WiFi模块上的金属外壳叫屏蔽罩,属于无线模块一个硬件设施之一,它的主要作用分为两个: 1.防止无线模块工作时对外界产生干扰和辐射;功率越大的无线模块产生的干扰和辐射也会相应的越大,所以加一个金属外壳可以在一定程度上减小这些干扰和辐射。 2.屏蔽外界对远距离WiFi模块产生干扰;在无线模块的工作环境当中,有很多复杂干扰源,如外界电场、磁场这种看不见也摸不着干扰源用存在着。但是,给无线模块加上屏蔽罩之后,就可以很好的隔绝了这些外界的干扰源。 那么屏蔽罩的工作原理是什么呢?用屏蔽罩将需要保护的继电器、芯片、单片机、电路板等重要功能元器件包围起来,从而形成一个保护圈,既可以有效防止无线模块产生的辐射干扰对外扩散,也可以防止外界干扰源对无线模块的正常工作产生干扰。 屏蔽罩的注意事项: 1.屏蔽罩并不是必需品,我们可以根据实际的情况来判断无线模块是否需要带屏蔽罩。例如考虑到成本、外观、实际设备使用情况等判断是否需要屏蔽罩。 2.使用屏蔽罩时,要考虑的因素有很多,例如屏蔽罩的尺寸大小、屏蔽罩离电子元器件的距离、屏蔽罩的材料等等,这些因素都是非常重要的;因为屏蔽罩设计的不够理想的话,很有可能会影响无线模块的性能。思为无线每一款无线模块上的屏蔽罩都是我司硬件工程师精心设计而成的,可以屏蔽大部分外界干扰,保证模块的正常工作。 总得来说,屏蔽罩对远距离WiFi模块是非常重要的,一是它可以提高无线模块的抗干扰能力,二是抗干扰能力越强也相对应的会提升模块的传输距离,所以无线模块加一个屏蔽罩外壳还是非常有必要的。但是,屏蔽罩并不是无线模块的必需品,这点在上文的注意事项中说得很清楚。  
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27
2022-09

智能家电wifi模组常见问题天线长度与频率波长的关系

发布时间: : 2022-09--27
智能家电wifi模组常见问题天线长度与频率波长的关系,智能家电wifi模组块在使用过程中,往往会遇见各种问题,今天整理了一份近几年来,客户常遇见的问题,希望能帮助到大家。 1. 智能家电wifi模组死机 1)查供电电源(电源负载电流是否比模块规格书上的发射电流大,电源类型) 2)是否影响到别的设备。(工作环境中,是否有其他的无线设备) 2. 智能家电wifi模组正常使用一段时间后,通讯距离越来越短怎么办? 这种情况,一般是硬件电路损坏,需要寄回维修。 3. 智能家电wifi模组发射不出信号或者通讯不上? 1)检查模块硬件接线是否有问题 2)看SPI是否能读寄存器值,如果是则说明接线正确,否则反之。 3)检查供电,是否达到工作电压(可通过降低功率确定) 4. 是否支持跳频功能? 不支持芯片自动跳频,需单片机设置频率 5. 同样的程序,在别的厂商的无线模块上可以正常工作,为什么我司的维修模块不能正常工作? 不同厂家的无线模块的天线、晶振不同,所以程序不一定匹配。 6. 我司的智能家电wifi模组是否能和别的厂商通讯? 实际的频率不一样,不能和别的厂商的无线模块通讯。(实际频率要用频谱仪测试) 7. 无线模块为什么发烫? 天线开关没有控制好。 8. 智能家电wifi模组怎么进入休眠状态? 用SPI接口发送指令,具体可参考我司对应的模块DOMO程序。 9. 无线模块怎么修改速率/频率?或某个无线模块速率/频率对应的参数值是多少? 每个无线模块都有寄存器手册或者配置软件,计算出需要修改的寄存器值,可通过SPI接口发送指令给无线模块 10. 智能家电wifi模组怎么设置功率? 每个无线模块的规格书都可以查看相对应的功率对照表。 11. 模块休眠时,为何接收不到数据? 无线模块在休眠状态时,是处于关闭无线的状态,这种情况下是无法接收数据 12. 无线模块如何从休眠中唤醒? 通过SPI接口发送任何指令。 13. 智能家电wifi模组如何实现无线远程唤醒? 除si4463模块有自带的LDC功能外,其他的前端无线模块都需单片机定时控制模块在休眠和接收中切换。 14. 无线模块一次可以发送多少字节? FSK系列模块的一次64字节,LORA系列模块一次255个字节,2.4G系列一次32个字节 15. 智能家电wifi模组如何实现大数据发送? 我们需要通过单片机设置好进行分包发送。 智能家电wifi模组常见的问题大概整理15条,希望能够帮助到大家。相关常见问题,也会近日整理出给到大家。如果您还有其他的问题欢迎联系我们。 天线长度与频率、波长的关系 天线在通信领域使用的范围很广,有的客户不知道天线长度和频率、波长有什么关系,天线长度的计算公式是什么,有时候看到网上卖的同频率的天线有长有短,心里疑惑不已,下面为大家分析天线长度与频率、波长的关系。 智能家电wifi模组天线长度与频率、波长的关系 天线长度与频率成反比,与波长成正比,频率越高,波长越短,天线也就可以做得越短。 天线长度计算公式 当天线的长度为波长的1/4时,天线的发射和接收转换效率高。 因此,天线的长度将根据所发射和接收信号的频率即波长来决定。用下面的公式可以计算出波长,然后将算出的波长除以4就是对应的佳天线长度。 频率与波长的换算公式为: 波长=30万公里/频率 =300000000米/频率 (得到的单位为米)) 例如:无线数传电台使用的信号频率为435MHz,波长为: 波长= 300000公里/435MHz = 300000000/435000000 = 300/435 = 0.69米 对应的天线长度应为 0.69/4 ,等于0.1725米 以上就是天线长度与频率|波长的关系,天线的长度中心工作频率的波长有直接关系,在购买的时候我们也许会发现天线似乎没有那么长,那是因为厂家用加感的方式缩短长度,如果把里面一圈圈的线材拉直,长度也是接近波长的四分之一的。
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