这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F350CBT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F350CBT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F350xx ARM® Cortex®-M4 32-bit MCU Datasheet General description The GD32F350xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support. The GD32F350xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five general 16-bit timers, a general 32-bit timer, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, an I2S, a HDMI-CEC, a TSI and an USBFS. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F350xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. Device information Table 2-1. GD32F350xx devices features and peripheral list   Part Number GD32F350xx   G4 G6 G8 K4 K6 K8 C4 C6 C8 CB R4 R6 R8 RB Flash Code area (KB)   16   32   64   16   32   64   16   32   64   64   16   32   64   64   Data area (KB)   0   0   0   0   0   0   0   0   0   64   0   0   0   64   Total (KB)   16   32   64   16   32   64   16   32   64   128   16   32   64   128 SRAM (KB) 4 6 8 4 6 8 4 6 8 16 4 8 16 16 Timers General timer (32-bit) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1)   General timer (16-bit) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16)   Advanced timer (16-bit) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0)   Basic timer (16-bit) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5)   SysTick
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F350CBT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F350xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

General description

The GD32F350xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support.
The GD32F350xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five general 16-bit timers, a general 32-bit timer, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, an I2S, a HDMI-CEC, a TSI and an USBFS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F350xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.

Device information

Table 2-1. GD32F350xx devices features and peripheral list

 

Part Number

GD32F350xx

 

G4

G6

G8

K4

K6

K8

C4

C6

C8

CB

R4

R6

R8

RB

Flash

Code area

(KB)

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

64

 

16

 

32

 

64

 

64

 

Data area

(KB)

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

64

 

0

 

0

 

0

 

64

 

Total

(KB)

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

128

 

16

 

32

 

64

 

128

SRAM (KB)

4

6

8

4

6

8

4

6

8

16

4

8

16

16

Timers

General timer

(32-bit)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

 

General timer

(16-bit)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

 

Advanced

timer (16-bit)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

 

Basic timer

(16-bit)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

 

SysTick

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Connectivity

 

USART

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

 

 

I2C

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

 

 

SPI/I2S

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

2/1

(0-1)/(0)

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

2/1

(0-1)/(0)

 

USBFS

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

HDMI-CEC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

GPIO

24

24

24

27

27

27

39

39

39

39

55

55

55

55

TSI

(Channels)

14

14

14

14

14

14

17

17

17

17

18

18

18

18

CMP

2

2

2

2

2

2

2

2

2

2

2

2

2

2

EXTI

16

16

16

16

16

16

16

16

16

16

16

16

16

16

 

 

Part Number

GD32F350xx

 

G4

G6

G8

K4

K6

K8

C4

C6

C8

CB

R4

R6

R8

RB

ADC

Units

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Channels

(External)

10

10

10

10

10

10

10

10

10

10

16

16

16

16

 

Channels

(Internal)

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

DAC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Package

QFN28

QFN32

LQFP48

LQFP64

 

Memory map

Table 2-2. GD32F350xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0xE000 0000 - 0xE00F FFFF

Cortex-M4 internal peripherals

External Device

 

0xA000 0000 - 0xDFFF FFFF

Reserved

External RAM

 

0x6000 0000 - 0x9FFF FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripherals

 

AHB1

0x5004 0000 - 0x5FFF FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

 

 

 

AHB2

0x4800 1800 - 0x4FFF FFFF

Reserved

 

 

0x4800 1400 - 0x4800 17FF

GPIOF

 

 

0x4800 1000 - 0x4800 13FF

Reserved

 

 

0x4800 0C00 - 0x4800 0FFF

GPIOD

 

 

0x4800 0800 - 0x4800 0BFF

GPIOC

 

 

0x4800 0400 - 0x4800 07FF

GPIOB

 

 

0x4800 0000 - 0x4800 03FF

GPIOA

 

 

 

 

 

 

 

AHB1

0x4002 4400 - 0x47FF FFFF

Reserved

 

 

0x4002 4000 - 0x4002 43FF

TSI

 

 

0x4002 3400 - 0x4002 3FFF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1400 - 0x4002 1FFF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0400 - 0x4002 0FFF

Reserved

 

 

0x4002 0000 - 0x4002 03FF

DMA

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 8000 - 0x4001 FFFF

Reserved

 

 

0x4001 5C00 - 0x4001 7FFF

Reserved

 

 

0x4001 4C00 - 0x4001 5BFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER16

 

 

0x4001 4400 - 0x4001 47FF

TIMER15

 

 

0x4001 4000 - 0x4001 43FF

TIMER14

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

Reserved

 

 

0x4001 3000 - 0x4001 33FF

SPI0/I2S0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

Reserved

 

 

0x4001 2400 - 0x4001 27FF

ADC

 

 

0x4001 0800 - 0x4001 23FF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

SYSCFG + CMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

CTC

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

CEC

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6400 - 0x4000 6FFF

Reserved

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 4800 - 0x4000 53FF

Reserved

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

Reserved

 

 

0x4000 3800 - 0x4000 3BFF

SPI1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1400 - 0x4000 1FFF

Reserved

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0800 - 0x4000 0FFF

Reserved

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

SRAM

 

0x2000 4000 - 0x3FFF FFFF

Reserved

 

 

0x2000 0000 - 0x2000 3FFF

SRAM

 

 

 

Code

 

0x1FFF FC00 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF FBFF

Option bytes

 

 

0x1FFF EC00 - 0x1FFF F7FF

System memory

 

 

0x0810 0000 - 0x1FFF EBFF

Reserved

 

 

0x0800 0000 - 0x0801 FFFF

Main Flash memory

 

 

0x0010 0000 - 0x07FF FFFF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x0000 0000 - 0x000F FFFF

Aliased to Flash or system memory

GD32F350Rx LQFP64 pin definitions

Table 2-3. GD32F350Rx LQFP64 pin definitions

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13- TAMPER-

RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

PF0-OSCIN

 

5

 

I/O

 

5VT

Default: PF0

Alternate: CTC_SYNC Additional: OSCIN

PF1- OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

 

PC0

 

8

 

I/O

 

Default: PC0

Alternate: EVENTOUT Additional: ADC_IN10

 

PC1

 

9

 

I/O

 

Default: PC1

Alternate: EVENTOUT Additional: ADC_IN11

 

PC2

 

10

 

I/O

 

Default: PC2 Alternate: EVENTOUT

Additional: ADC_IN12

 

PC3

 

11

 

I/O

 

Default: PC3 Alternate: EVENTOUT

Additional: ADC_IN13

VSSA

12

P

 

Default: VSSA

VDDA

13

P

 

Default: VDDA

 

 

 

PA0-WKUP

 

 

 

14

 

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL(5)

Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1,

WKUP0

 

 

PA1

 

 

15

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1, CMP0_IP

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PA2

 

 

 

 

Alternate: USART0_TX(3), USART1_TX(4),

PA2

16

I/O

 

TIMER1_CH2, TIMER14_CH0 ,

 

 

 

 

CMP1_OUT,TSI_G0_IO2

 

 

 

 

Additional: ADC_IN2, CMP1_IM6

 

 

 

 

Default: PA3

PA3

17

I/O

 

Alternate: USART0_RX(3), USART1_RX(4),

TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3

 

 

 

 

Additional: ADC_IN3, CMP1_IP

 

PF4

 

18

 

I/O

 

5VT

Default: PF4

Alternate: EVENTOUT

 

PF5

 

19

 

I/O

 

5VT

Default: PF5

Alternate: EVENTOUT

 

 

 

 

Default: PA4

 

 

 

 

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),

PA4

20

I/O

 

USART1_CK(4), TIMER13_CH0, TSI_G1_IO0,

SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4, CMP0_IM4, CMP1_IM4,

 

 

 

 

DAC0_OUT

 

 

 

 

Default: PA5

PA5

21

I/O

 

Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0,

TIMER1_ETI, TSI_G1_IO1

 

 

 

 

Additional: ADC_IN5, CMP0_IM5, CMP1_IM5

 

 

 

 

Default: PA6

 

 

 

 

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,

PA6

22

I/O

 

TIMER0_BKIN, TIMER15_CH0, CMP0_OUT,

 

 

 

 

TSI_G1_IO2, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,

PA7

23

I/O

 

TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,

 

 

 

 

CMP1_OUT, TSI_G1_IO3, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PC4

PC4

24

I/O

 

Alternate: EVENTOUT

 

 

 

 

Additional: ADC_IN14

 

 

 

 

Default: PC5

PC5

25

I/O

 

Alternate: TSI_G2_IO0

 

 

 

 

Additional: ADC_IN15, WKUP4

 

 

 

 

Default: PB0

PB0

26

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

TSI_G2_IO1, USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

27

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

 

 

 

 

TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK(5)

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Additional: ADC_IN9

 

PB2

 

28

 

I/O

 

5VT

Default: PB2

Alternate: TSI_G2_IO3

 

 

 

 

Default: PB10

PB10

29

I/O

5VT

Alternate: I2C0_SCL(3),I2C1_SCL(5), CEC,

 

 

 

 

TIMER1_CH2, TSITG, SPI1_IO2(5)

 

 

 

 

Default: PB11

PB11

30

I/O

5VT

Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3,

 

 

 

 

TSI_G5_IO0, EVENTOUT, SPI1_IO3(5)

VSS

31

P

 

Default: VSS

VDD

32

P

 

Default: VDD

 

 

 

 

Default: PB12

PB12

33

I/O

5VT

Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN,

 

 

 

 

TSI_G5_IO1, I2C1_SMBA(5), EVENTOUT

 

 

 

 

Default: PB13

PB13

34

I/O

5VT

Alternate: SPI0_SCK(3), SPI1_SCK(5),

 

 

 

 

TIMER0_CH0_ON, TSI_G5_IO2

 

 

 

 

Default: PB14

PB14

35

I/O

5VT

Alternate: SPI0_MISO(3), SPI1_MISO(5),

 

 

 

 

TIMER0_CH1_ON, TIMER14_CH0, TSI_G5_IO3

 

 

 

 

Default: PB15

 

 

 

 

Alternate: SPI0_MOSI(3), SPI1_MOSI(5),

PB15

36

I/O

5VT

TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

PC6

 

37

 

I/O

 

5VT

Default: PC6

Alternate: TIMER2_CH0, I2S0_MCK

 

PC7

 

38

 

I/O

 

5VT

Default: PC7

Alternate: TIMER2_CH1

 

PC8

 

39

 

I/O

 

5VT

Default: PC8

Alternate: TIMER2_CH2

 

PC9

 

40

 

I/O

 

5VT

Default: PC9

Alternate: TIMER2_CH3

 

 

 

 

Default: PA8

PA8

41

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,USBFS_SOF,CTC_SYNC

 

 

 

 

Default: PA9

PA9

42

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN,

 

 

 

 

TSI_G3_IO0, I2C0_SCL,USBFS_VBUS

 

 

 

 

Default: PA10

PA10

43

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

TSI_G3_IO1, I2C0_SDA, USBFS_ID

 

 

 

 

Default: PA11

PA11

44

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT,

TSI_G3_IO2, EVENTOUT, SPI1_IO2(5)

 

 

 

 

Additional: USBFS_DM

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PA12

PA12

45

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT,

TSI_G3_IO3, EVENTOUT, SPI1_IO3(5)

 

 

 

 

Additional: USBFS_DP

 

PA13

 

46

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PF6

 

47

 

I/O

 

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

 

PF7

 

48

 

I/O

 

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

 

 

 

 

Default: PA14

PA14

49

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

50

I/O

5VT

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

USART1_RX(4), TIMER1_CH0, TIMER1_ETI,

 

 

 

 

SPI1_NSS(5), EVENTOUT

PC10

51

I/O

5VT

Default: PC10

PC11

52

I/O

5VT

Default: PC11

PC12

53

I/O

5VT

Default: PC12

 

PD2

 

54

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI

 

 

 

 

Default: PB3

PB3

55

I/O

5VT

Alternate: SPI0_SCK, I2S0_CK, TIMER1_CH1,

 

 

 

 

TSI_G4_IO0, EVENTOUT

 

 

 

 

Default: PB4

PB4

56

I/O

5VT

Alternate: SPI0_MISO,I2S0_MCK, TIMER2_CH0,

 

 

 

 

TSI_G4_IO1, EVENTOUT

 

 

 

 

Default: PB5

PB5

57

I/O

5VT

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA,

TIMER15_BKIN, TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

 

 

 

Default: PB6

PB6

58

I/O

5VT

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON,

 

 

 

 

TSI_G4_IO2

 

 

 

 

Default: PB7

PB7

59

I/O

5VT

Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,T

 

 

 

 

SI_G4_IO3

BOOT0

60

I

 

Default: BOOT0

 

PB8

 

61

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG

 

 

 

 

Default: PB9

PB9

62

I/O

5VT

Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,

 

 

 

 

EVENTOUT, I2S0_MCK

VSS

63

P

 

Default: VSS

 

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

VDD

64

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F350R4 devices only.
(4)Functions are available on GD32F350RB/8/6 devices.
(5)Functions are available on GD32F350RB/8 devices.

GD32F350Cx LQFP48 pin definitions

Table 2-4. GD32F350Cx LQFP48 pin definitions

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13- TAMPER-

RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

PF0-OSCIN

 

5

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1-

OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

VSSA

8

P

 

Default: VSSA

VDDA

9

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

10

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL(5)

Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1, WKUP0

 

 

PA1

 

 

11

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1, CMP0_IP

 

 

PA2

 

 

12

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 , CMP1_OUT,TSI_G0_IO2

Additional: ADC_IN2, CMP1_IM6

PA3

13

I/O

 

Default: PA3

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: USART0_RX(3), USART1_RX(4),

 

 

 

 

TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3

 

 

 

 

Additional: ADC_IN3, CMP1_IP

 

 

 

 

Default: PA4

 

 

 

 

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),

PA4

14

I/O

 

USART1_CK(4), TIMER13_CH0, TSI_G1_IO0,

SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4, CMP0_IM4, CMP1_IM4,

 

 

 

 

DAC0_OUT

 

 

 

 

Default: PA5

PA5

15

I/O

 

Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0,

TIMER1_ETI, TSI_G1_IO1

 

 

 

 

Additional: ADC_IN5, CMP0_IM5, CMP1_IM5

 

 

 

 

Default: PA6

 

 

 

 

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,

PA6

16

I/O

 

TIMER0_BKIN, TIMER15_CH0, CMP0_OUT,

 

 

 

 

TSI_G1_IO2, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,

PA7

17

I/O

 

TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,

 

 

 

 

CMP1_OUT, TSI_G1_IO3, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

18

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

TSI_G2_IO1, USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

19

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

 

PB2

 

20

 

I/O

 

5VT

Default: PB2

Alternate: TSI_G2_IO3

 

 

 

 

Default: PB10

PB10

21

I/O

5VT

Alternate: I2C0_SCL(3),I2C1_SCL(5), CEC, TIMER1_CH2,

 

 

 

 

TSITG, SPI1_IO2(5)

 

 

 

 

Default: PB11

PB11

22

I/O

5VT

Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3,

 

 

 

 

TSI_G5_IO0, EVENTOUT, SPI1_IO3(5)

VSS

23

P

 

Default: VSS

VDD

24

P

 

Default: VDD

 

 

 

 

Default: PB12

PB12

25

I/O

5VT

Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN,

 

 

 

 

TSI_G5_IO1, I2C1_SMBA(5), EVENTOUT

PB13

26

I/O

5VT

Default: PB13

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON,

 

 

 

 

TSI_G5_IO2

 

 

 

 

Default: PB14

PB14

27

I/O

5VT

Alternate: SPI0_MISO(3), SPI1_MISO(5),

 

 

 

 

TIMER0_CH1_ON, TIMER14_CH0, TSI_G5_IO3

 

 

 

 

Default: PB15

 

PB15

 

28

 

I/O

 

5VT

Alternate: SPI0_MOSI(3), SPI1_MOSI(5),

TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

 

 

 

Default: PA8

PA8

29

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,USBFS_SOF,CTC_SYNC

 

 

 

 

Default: PA9

PA9

30

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN,

 

 

 

 

TSI_G3_IO0, I2C0_SCL,USBFS_VBUS

 

 

 

 

Default: PA10

PA10

31

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

TSI_G3_IO1, I2C0_SDA, USBFS_ID

 

 

 

 

Default: PA11

PA11

32

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT,

TSI_G3_IO2, EVENTOUT, SPI1_IO2(5)

 

 

 

 

Additional: USBFS_DM

 

 

 

 

Default: PA12

PA12

33

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT,

TSI_G3_IO3, EVENTOUT, SPI1_IO3(5)

 

 

 

 

Additional: USBFS_DP

 

PA13

 

34

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PF6

 

35

 

I/O

 

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

 

PF7

 

36

 

I/O

 

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

 

 

 

 

Default: PA14

PA14

37

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

38

I/O

5VT

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

USART1_RX(4), TIMER1_CH0, TIMER1_ETI,

 

 

 

 

SPI1_NSS(5), EVENTOUT

 

 

 

 

Default: PB5

PB5

41

I/O

5VT

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA,

TIMER15_BKIN, TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

PB6

 

42

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON,

 

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

 

 

 

 

TSI_G4_IO2

 

PB7

 

43

 

I/O

 

5VT

Default: PB7 Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,T

SI_G4_IO3

BOOT0

44

I

 

Default: BOOT0

 

PB8

 

45

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG

 

PB9

 

46

 

I/O

 

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,

EVENTOUT, I2S0_MCK

VSS

47

P

 

Default: VSS

VDD

48

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F350C4 devices only.
(4)Functions are available on GD32F350CB/8/6 devices.
(5)Functions are available on GD32F350CB/8 devices.

GD32F350Kx QFN32 pin definitions

Table 2-5. GD32F350Kx QFN32 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1-

OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

6

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL(5)

Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1, WKUP0

 

 

PA1

 

 

7

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1, CMP0_IP

 

 

PA2

 

 

8

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 , CMP1_OUT,TSI_G0_IO2

Additional: ADC_IN2, CMP1_IM6

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PA3

PA3

9

I/O

 

Alternate: USART0_RX(3), USART1_RX(4),

TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3

 

 

 

 

Additional: ADC_IN3, CMP1_IP

 

 

 

 

Default: PA4

 

 

 

 

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),

PA4

10

I/O

 

USART1_CK(4), TIMER13_CH0, TSI_G1_IO0,

SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4, CMP0_IM4, CMP1_IM4,

 

 

 

 

DAC0_OUT

 

 

 

 

Default: PA5

PA5

11

I/O

 

Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0,

TIMER1_ETI, TSI_G1_IO1

 

 

 

 

Additional: ADC_IN5, CMP0_IM5, CMP1_IM5

 

 

 

 

Default: PA6

 

 

 

 

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,

PA6

12

I/O

 

TIMER0_BKIN, TIMER15_CH0, CMP0_OUT,

 

 

 

 

TSI_G1_IO2, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,

PA7

13

I/O

 

TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,

 

 

 

 

CMP1_OUT, TSI_G1_IO3, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

14

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

TSI_G2_IO1, USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

15

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

 

PB2

 

16

 

I/O

 

5VT

Default: PB2

Alternate: TSI_G2_IO3

VDD

17

P

 

Default: VDD

 

 

 

 

Default: PA8

PA8

18

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,USBFS_SOF,CTC_SYNC

 

 

 

 

Default: PA9

PA9

19

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN,

 

 

 

 

TSI_G3_IO0, I2C0_SCL,USBFS_VBUS

 

 

 

 

Default: PA10

PA10

20

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

TSI_G3_IO1, I2C0_SDA, USBFS_ID

 

PA11

 

21

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT,

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

TSI_G3_IO2, EVENTOUT, SPI1_IO2(5)

 

 

 

 

Additional: USBFS_DM

 

 

 

 

Default: PA12

PA12

22

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT,

TSI_G3_IO3, EVENTOUT, SPI1_IO3(5)

 

 

 

 

Additional: USBFS_DP

 

PA13

 

23

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

 

 

 

Default: PA14

PA14

24

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

25

I/O

5VT

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

USART1_RX(4), TIMER1_CH0, TIMER1_ETI,

 

 

 

 

SPI1_NSS(5), EVENTOUT

 

 

 

 

Default: PB3

PB3

26

I/O

5VT

Alternate: SPI0_SCK, I2S0_CK, TIMER1_CH1,

 

 

 

 

TSI_G4_IO0, EVENTOUT

 

 

 

 

Default: PB4

PB4

27

I/O

5VT

Alternate: SPI0_MISO,I2S0_MCK, TIMER2_CH0,

 

 

 

 

TSI_G4_IO1, EVENTOUT

 

 

 

 

Default: PB5

PB5

28

I/O

5VT

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA,

TIMER15_BKIN, TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

 

 

 

Default: PB6

PB6

29

I/O

5VT

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON,

 

 

 

 

TSI_G4_IO2

 

 

 

 

Default: PB7

PB7

30

I/O

5VT

Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,T

 

 

 

 

SI_G4_IO3

BOOT0

31

I

 

Default: BOOT0

 

PB8

 

32

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG

VDD

1

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F350K4 devices only.
(4)Functions are available on GD32F350K8/6 devices.
(5)Functions are available on GD32F350K8 devices.

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 128 Kbytes of Flash memory
Up to 16 Kbytes of SRAM with hardware parity checking

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash and 16 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. Table 2-2. GD32F350xx memory map shows the memory map of the GD32F350xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

3.3Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 108 MHz/54 MHz/54 MHz. See Figure 2-6. GD32F350xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15).

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, CMP0/CMP1 output, LVD output, USART wakeup, CEC wakeup and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.86 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage (VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx)

and the advanced timer (TIMER0) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

7 channel DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC and I2S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 55 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 55 general purpose I/O pins (GPIO) in GD32F350xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push- pull open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.

All GPIOs are high-current capable except for analog inputs.


Timers and PWM generation

One 16-bit advanced timer (TIMER0), one 32-bit general timer (TIMER1), five 16-bit general timers (TIMER2, TIMER13 ~ TIMER16), and one 16-bit basic timer (TIMER5)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5, is mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F350xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month
automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to two SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to two USARTs with operating frequency up to 6.75 MB/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

One I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI0
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F350xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI0. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.

HDMI CEC

Hardware support Consumer Electronics Control (CEC) protocol (HDMI standard rev1.4)

The CEC protocol provides high-level control functions between the audiovisual products linked with HDMI cables. GD32F350xx contain a HDMI-CEC controller which has an independent clock domain and can wake up the MCU from deep-sleep mode on data reception.

Universal serial bus full-speed interface (USBFS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator (IRC48M) support crystal-less operation
Internal main PLL for USB CLK compliantly
Internal USBFS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) or by the internal 48 MHz oscillator (IRC48M) in automatic trimming mode that allows crystal-less operation.

Touch sensing interface (TSI)

Charge transfer sequence fully controlled by hardware
6 fully parallel groups implemented
18 IOs configurable for capacitive sensing Channel Pins and 6 for Sample Pins
Configurable transfer sequence frequency
Able to implement the user specific charge transfer sequences
Sequence end and error flags / configurable interrupts
Spread spectrum function implemented

Capacitive sensing technology can be used for the detection of a finger (or any conductive object) presence near an electrode. The capacitive variation of the electrode introduced by the finger can be measured by charging and detecting the voltage across the sampling capacitor. GD32F350xx contain a hardware touch sensing interface (TSI) and only requires few external components to operate. The sensing channels are distributed over 6 analog I/O groups including: Group0 (PA0 ~ PA3), Group1 (PA4 ~ PA7), Group2 (PC5, PB0 ~ PB2),

Group3 (PA9 ~ PA12), Group4 (PB3, PB4, PB6, PB7) and Group5 (PB11 ~ PB14),


Comparators (CMP)

Two fast rail-to-rail low-power comparators with software configurable
Programmable reference voltage (internal, external I/O or DAC output pin)

Two Comparators (CMP) are implemented within the devices. Both comparators can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP64 (GD32F350Rx), LQFP48 (GD32F350Cx), QFN32 (GD32F350Kx) and QFN28 (GD32F350Gx)
Operation temperature range: -40°C to +85°C (industrial level)

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18
2022-02

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

发布时间: : 2022-02--18
uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗,指纹门锁并不是什么新鲜事,我相信每个人都很熟悉。随着近年来智能家居的逐步普及,指纹门锁也进入了成千上万的家庭。今天的功耗雷达模块指纹门锁不仅消除了繁琐的钥匙,而且还提供了各种智能功能,uA级别智能门锁低功耗雷达模块用在智能门锁上,可以实现门锁的智能感应屏幕,使电池寿命延长3-5倍,如与其他智能家居连接,成为智能场景的开关。所以今天的指纹门锁更被称为智能门锁。 今天,让我们来谈谈功耗雷达模块智能门锁的安全性。希望能让更多想知道智能门锁的朋友认识下。 指纹识别是智能门锁的核心 指纹识别技术在我们的智能手机上随处可见。从以前的实体指纹识别到屏幕下的指纹识别,可以说指纹识别技术已经相当成熟。指纹识别可以说是整个uA级低功耗雷达模块智能门锁的核心。 目前主要有三种常见的指纹识别方法,即光学指纹识别、半导体指纹识别和超声指纹识别。 光学指纹识别 让我们先谈谈光学指纹识别的原理实际上是光的反射。我们都知道指纹本身是不均匀的。当光照射到我们的指纹上时,它会反射,光接收器可以通过接收反射的光来绘制我们的指纹。就像激光雷达测绘一样。 光学指纹识别通常出现在打卡机上,手机上的屏幕指纹识别技术也使用光学指纹识别。今天的光学指纹识别已经达到了非常快的识别速度。 然而,光学指纹识别有一个缺点,即硬件上的活体识别无法实现,容易被指模破解。通常,活体识别是通过软件算法进行的。如果算法处理不当,很容易翻车。 此外,光学指纹识别也容易受到液体的影响,湿手解锁的成功率也会下降。 超声指纹识别 超声指纹识别也被称为射频指纹识别,其原理与光学类型相似,但超声波使用声波反射,实际上是声纳的缩小版本。因为使用声波,不要担心水折射会降低识别率,所以超声指纹识别可以湿手解锁。然而,超声指纹识别在防破解方面与光学类型一样,不能实现硬件,可以被指模破解,活体识别仍然依赖于算法。 半导体指纹识别 半导体指纹识别主要采用电容、电场(即我们所说的电感)、温度和压力原理来实现指纹图像的收集。当用户将手指放在前面时,皮肤形成电容阵列的极板,电容阵列的背面是绝缘极板。由于不同区域指纹的脊柱与谷物之间的距离也不同,因此每个单元的电容量随之变化,从而获得指纹图像。半导体指纹识别具有价格低、体积小、识别率高的优点,因此大多数uA级低功耗雷达模块智能门锁都采用了这种方案。半导体指纹识别的另一个功能是活体识别。传统的硅胶指模无法破解。 当然,这并不意味着半导体可以百分识别活体。所谓的半导体指纹识别活体检测不使用指纹活体体征。本质上,它取决于皮肤的材料特性,这意味着虽然传统的硅胶指模无法破解。 一般来说,无论哪种指纹识别,都有可能被破解,只是说破解的水平。然而,今天的指纹识别,无论是硬件生活识别还是算法生活识别,都相对成熟,很难破解。毕竟,都可以通过支付级别的认证,大大保证安全。 目前,市场上大多数智能门锁仍将保留钥匙孔。除了指纹解锁外,用户还可以用传统钥匙开门。留下钥匙孔的主要目的是在指纹识别故障或智能门锁耗尽时仍有开门的方法。但由于有钥匙孔,它表明它可以通过技术手段解锁。 目前市场上的锁等级可分为A、B、C三个等级,这三个等级主要是通过防暴开锁和防技术开锁的程度来区分的。A级锁要求技术解锁时间不少于1分钟,B级锁要求不少于5分钟。即使是高级别的C级锁也只要求技术解锁时间不少于10分钟。 也就是说,现在市场上大多数门锁,无论是什么级别,在专业的解锁大师面前都糊,只不过是时间长短。 安全是重要的,是否安全增加了人们对uA级别低功耗雷达模块智能门锁安全的担忧。事实上,现在到处都是摄像头,强大的人脸识别,以及移动支付的出现,使家庭现金减少,所有这些都使得入室盗窃的成本急剧上升,近年来各省市的入室盗窃几乎呈悬崖状下降。 换句话说,无论锁有多安全,无论锁有多难打开,都可能比在门口安装摄像头更具威慑力。 因此,担心uA级别低功耗雷达模块智能门锁是否不安全可能意义不大。毕竟,家里的防盗锁可能不安全。我们应该更加关注门锁能给我们带来多少便利。 我们要考虑的是智能门锁的兼容性和通用性。毕竟,智能门锁近年来才流行起来。大多数人在后期将普通机械门锁升级为智能门锁。因此,智能门锁能否与原门兼容是非常重要的。如果不兼容,发现无法安装是一件非常麻烦的事情。 uA级别低功耗雷达模块智能门锁主要是为了避免带钥匙的麻烦。因此,智能门锁的便利性尤为重要。便利性主要体现在指纹的识别率上。手指受伤导致指纹磨损或老年人指纹较浅。智能门锁能否识别是非常重要的。 当然,如果指纹真的失效,是否有其他解锁方案,如密码解锁或NFC解锁。还需要注意密码解锁是否有虚假密码等防窥镜措施。 当然,智能门锁的耐久性也是一个需要特别注意的地方。uA级别低功耗雷达模块智能门锁主要依靠内部电池供电,这就要求智能门锁的耐久性尽可能好,否则经常充电或更换电池会非常麻烦。 智能门锁低功耗雷达模块:让门锁更加智能省电节约功耗 在当今信息化时代,智能门锁已经成为人们生活中不可或缺的一部分。对于门锁制造商来说,如何提高门锁的安全性、实用性和便利性,成为他们面对的重要课题。随着人们对门锁智能化的需求越来越高,门锁的能耗问题也成为了门锁制造商需要重视的问题。为此,越来越多的门锁制造商开始推出以低功耗为主题的系列产品。在这样的背景下,智能门锁低功耗雷达模块应运而生。 智能门锁低功耗雷达模块是一种新型技术,其采取雷达技术对门锁周围的物体进行探测,一旦发现门锁附近有人靠近,便会将门锁自动解锁,无需使用钥匙。同时,在保持智能控制的前提下,实现了门锁省电、节约功耗,延长门锁使用寿命。 在使用智能门锁低功耗雷达模块的门锁中,控制电路和自动解锁机制是关键的部件。控制电路采用先进的芯片技术,通过优秀的功耗控制以实现模块化管理。而自动解锁机制不仅可以通过微波信号控制实现门锁的无钥匙解锁,还能够在门锁未处理的情况下自动锁定,保障门锁的安全。 智能门锁低功耗雷达模块的主要特点是:低功耗、高灵敏度和高可靠性。该模块在进行人体检测时,可以远距离探测到距离为5-7米远处的人体信号,目标检测速度极快,而且对门锁周围的环境要求不高。同时,该模块采用了自适应自动补偿技术,能够根据不同环境的变化自动调整信号发射和接收参数,减小误检率。 在使用智能门锁低功耗雷达模块的门锁中,其功耗可以做到非常低,一组电池能够支持门锁持续使用几年左右。而且这样的智能门锁除了具有自动解锁的功能,还可与APP相互匹配,实现了远程操作的便捷性。 总的来说,智能门锁低功耗雷达模块的问世,解决了门锁安全性和省电节省方面的问题,是智能门锁材料不可或缺的一部分。作为门锁制造商,只有不断创新,利用这种新型技术,将会在行业中占据重要的地位。 除了上文所述的主要特点和优势,智能门锁低功耗雷达模块还具有以下几点: 1. 实时监测门锁周围环境变化,通过物体的距离体积和运动来确定是否有人靠近门锁,并控制门锁的开启或关闭,使得门锁更加智能化。 2. 可对门锁附件进行检测,如门挂、门应急照明灯以及紧急呼叫按钮等,并及时给出响应,确保门锁能够正常运作。这样,门锁在不受干扰的情况下,能够 保持安全通道。 3. 通过智能学习技术,能够自适应网站多种环境的变化,让智能门锁低功耗雷达模块更加准确和精细的控制门锁的开关,节约能耗并延长使用寿命。 4. 能够与其他智能电器相连,如智能家居系统、电视等,形成智能家居生态圈,更好地控制家庭访客进出,让生活更加方便。 综上所述,智能门锁低功耗雷达模块的出现,对提升门锁能耗管理和智能化有着重要作用。门锁制造商只有将这些新型技术运用到门锁产品中,才能更加贴合用户需求,满足消费市场的日益增长的智能化需求。
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14
2022-01

微波雷达传感器雷达感应浴室镜上的应用

发布时间: : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用,如今,家用电器的智能化已成为一种常态,越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入,今天就来说说这个话题。 什么是智能浴室镜?智慧型浴室镜,顾名思义,就是卫浴镜子智能化升级,入门级产品基本具备了彩灯和镜面触摸功能,更高档次的产品安装有微波雷达传感器智能感应,当感应到有人接近到一定距离即可开启亮灯或者亮屏操作,也可三色无极调,智能除雾,语音交互,日程安排备忘,甚至在镜子上看电视,听音乐,气象预报,问题查询,智能控制,健康管理等。 智能化雷达感应浴室镜与普通镜的区别,为什么要选TA?,就功能而言,普通浴镜价格用它没有什么压力!而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言,普通浴镜功能单一,而微波雷达传感器智能浴室镜功能创新:镜子灯光色温和亮度可以自由调节,镜面还可以湿手触控,智能除雾,既环保又健康! 尽管智能浴镜比较新颖,但功能丰富,体验感更好,特别是入门级的智能浴镜,具有基础智能化功能,真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么? ①确定智能浴室镜的安装位置,因为是安装时在墙壁上打孔,一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时,根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后,在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度,一般智能浴镜的标准安装高度约85cm(从地砖到镜子底),具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍,可用酒精或30%清洁稀释液擦洗,平时可用干毛巾养护,注意多通风。
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23
2024-02

雷达感应模块测评人体感应控制器智能家居中的应用与价值

发布时间: : 2024-02--23
引言 在当今的智能化时代,雷达感应模块和人体感应控制器已经成为了生活中不可或缺的一部分。雷达感应模块以其独特的非接触、高精度和快速响应特点,在人体感应控制器中发挥着核心作用。随着科技的不断发展,雷达感应模块和人体感应控制器在智能化领域的应用越来越广泛,为人们的生活带来了诸多便利。 雷达感应模块的工作原理 雷达技术是一种利用无线电波探测目标的技术。雷达感应模块则是基于雷达技术研发的一种传感器,通过发射和接收高频电磁波来检测周围物体的移动。其工作原理主要包括发射、反射、接收和信号处理四个环节。雷达感应模块通常采用微波雷达技术,其发射的电磁波频率较高,能够实现高精度、远距离的探测。与其他传感器相比,雷达感应模块具有更强的抗干扰能力、更远的探测距离和更高的精度。 人体感应控制器的基本原理和应用 人体感应技术是一种利用微波技术检测人体存在的技术。人体感应控制器则是将人体感应技术与日常生活用品相结合的一种智能化设备。其基本原理是利用传感器检测人体的移动或存在,并通过相应的控制逻辑实现自动化控制。人体感应控制器广泛应用于智能家居、智能安防、智能照明等领域,为人们的生活带来便利和舒适。 雷达感应模块在人体感应控制器中的优势 雷达感应模块在人体感应控制器中具有许多优势。首先,雷达感应模块的探测距离较远,能够实现远距离的人体移动探测。其次,雷达感应模块不受环境光线的限制,即使在黑暗环境下也能正常工作。此外,雷达感应模块还具有较高的精度和响应速度,能够快速准确地检测人体的移动。这些优势使得雷达感应模块在人体感应控制器中具有更高的应用价值,能够满足各种复杂场景的需求。 实际产品评测 为了全面了解雷达感应模块在人体感应控制器中的应用效果,进行实际产品评测是必要的。在评测过程中,应选择市场上具有代表性的雷达感应模块和人体感应控制器产品,以确保评测结果的客观性和准确性。评测标准应包括探测距离、精度、响应速度、环境适应性等方面。通过实际测试和比较,可以得出雷达感应模块在人体感应控制器中的实际表现和应用效果,为消费者提供有价值的参考信息。 未来展望与结论 随着科技的不断发展,雷达感应模块和人体感应控制器将会拥有更多的应用场景和功能。未来,我们期望看到更加高效、智能、环保的雷达感应模块和人体感应控制器出现,为人们的生活带来更多便利和舒适。同时,随着物联网、人工智能等技术的不断发展,雷达感应模块和人体感应控制器将会有更广泛的应用前景和价值。通过深入了解其工作原理、优势和应用效果,我们可以更好地把握其发展趋势,并为未来的技术进步和应用拓展提供有益的参考。总之,雷达感应模块在人体感应控制器中具有广泛的应用前景和重要的价值,值得我们深入研究和探讨。
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23
2024-02

小夜灯雷达模块定制人体感应防盗系统优势与前景

发布时间: : 2024-02--23
一、引言 在当今社会,家庭安全越来越受到人们的关注。小夜灯雷达模块定制人体感应防盗系统作为一种新兴的防盗技术,通过感应人体移动来预防盗窃事件的发生,为家庭安全提供了新的保障。本文将详细介绍小夜灯雷达模块定制人体感应防盗系统的原理、特点及应用。 二、小夜灯雷达模块的工作原理 雷达模块是一种利用电磁波探测目标的传感器。它通过发射电磁波并接收反射回来的信号,分析信号的时延和波形变化来判断目标的位置和移动。小夜灯雷达模块则是在此基础上,通过特定的算法和电路设计,实现了对人体移动的准确感应。其工作原理主要基于多普勒效应,即当雷达发射的电磁波遇到移动物体时,反射回来的信号会发生频率变化,通过分析这种频率变化即可判断出物体的移动速度和方向。 三、定制人体感应防盗系统的特点 该系统通过小夜灯雷达模块对人体移动的准确感应,实时监测家庭成员的动态。一旦感应到异常人体移动,系统会立即触发报警装置,向用户发送警报信息,同时采取相应的防护措施,如启动家用电器的电源、控制智能门锁等,从而起到防盗的作用。该系统还具有易用性高、稳定性强的特点,可广泛应用于家庭、办公室等场所。 四、小夜灯雷达模块的实际应用案例 近年来,小夜灯雷达模块定制人体感应防盗系统在国内外市场得到了广泛应用。例如,一些家庭在卧室安装了该系统,当夜间有人非法闯入时,系统会立即触发报警装置并发送警报信息到用户的手机上,有效减少了入室盗窃事件的发生。此外,该系统还被应用于办公室、仓库等场所,为企业的财产安全提供了有力保障。 五、如何选择合适的小夜灯雷达模块定制人体感应防盗系统 在选择小夜灯雷达模块定制人体感应防盗系统时,用户需要考虑以下几个因素:首先,要选择知名品牌和优质产品,以确保系统的可靠性和稳定性;其次,要根据实际需求选择合适的感应距离和感应角度;此外,还需考虑系统的安装方式和维护成本等。在购买时,建议用户多方比较、慎重选择。 六、系统安装与维护 安装小夜灯雷达模块定制人体感应防盗系统时,需遵循简单的步骤,并确保遵循安全规范。安装完成后,用户还需定期进行系统检查和维护,以确保系统的正常运行和延长使用寿命。同时,在使用过程中如遇到问题或故障,可参考产品说明书或联系专业人员进行维修处理。 七、结论 综上所述,小夜灯雷达模块定制人体感应防盗系统作为一种新型的家庭安全防护技术,具有高精度、高稳定性、易用性强的特点。随着智能家居市场的不断发展壮大和人们安全意识的提高,该系统将会越来越受到用户的青睐和广泛应用。在未来,相信小夜灯雷达模块定制人体感应防盗系统将会在家庭安全防护领域发挥更加重要的作用。
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22
2024-02

雷达微波处理模块人体移动感应器:工作原理、应用与未来发展

发布时间: : 2024-02--22
一、引言 随着科技的进步,人体移动感应技术在智能家居、智能交通等领域的应用越来越广泛。雷达微波处理模块人体移动感应器作为其中的重要组成部分,受到了广泛的关注。本文将详细介绍雷达微波处理模块人体移动感应器的工作原理、应用领域及未来发展趋势。 二、雷达微波处理模块人体移动感应器的工作原理 雷达微波处理模块人体移动感应器利用雷达微波的特性,能够非接触地感知周围环境中的人体移动。雷达微波是一种无线电波,其波长在无线电波和红外线之间。当雷达微波遇到人体时,会反射回来,被接收器接收。通过对反射回来的微波进行信号处理,可以准确地检测到人体的移动。与传统的红外传感器相比,雷达微波传感器具有更远的探测距离和更高的灵敏度。 三、雷达微波处理模块人体移动感应器的应用领域 智能家居:雷达微波处理模块人体移动感应器在智能家居领域的应用非常广泛。例如,它可以用于节能,通过检测人体的移动来控制家中设备的开关,实现节能的目的。此外,它还可以用于安全监控,通过检测人体的移动,实现对家中异常情况的实时监测。 智能交通:雷达微波处理模块人体移动感应器在智能交通领域也有着广泛的应用。例如,它可以用于行人检测,帮助自动驾驶车辆实现安全行驶。此外,它还可以用于车辆流量监控,为交通管理部门提供实时的道路交通情况。 智能家居:雷达微波处理模块人体移动感应器在家居领域的应用也越来越广泛。例如,它可以用于跌倒检测,通过检测人体的移动变化,判断是否发生了跌倒事件。此外,它还可以用于睡眠监测,通过分析人体的呼吸和运动情况,评估睡眠质量。 其他领域:除了上述应用领域外,雷达微波处理模块人体移动感应器在其他领域也有着广泛的应用前景。例如,它可以用于智能安防、智慧城市等领域的人体行为分析、运动跟踪等。 四、雷达微波处理模块人体移动感应器的未来发展 随着技术的不断进步和应用需求的不断增长,雷达微波处理模块人体移动感应器的未来发展前景非常广阔。未来,雷达微波处理模块将进一步小型化、集成化,提高检测精度和稳定性。同时,随着人工智能技术的发展,雷达微波处理模块将与人工智能技术相结合,实现对人体行为的智能分析和预测。此外,随着物联网、云计算等技术的发展,雷达微波处理模块将实现更广泛的应用和数据共享。 五、结论 雷达微波处理模块人体移动感应器作为一种先进的感知技术,在各个领域都有着广泛的应用前景。随着技术的不断进步和应用需求的不断增长,未来雷达微波处理模块将实现更加多样化、智能化的应用。企业和研究机构应抓住这一技术发展的机遇,加强研发和应用推广,推动雷达微波处理模块人体移动感应器的普及和发展。
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