这是描述信息
兆易创新GD32-GigaDevice-兆易创新代理

兆易创新GD32F350CBT6-GD32 ARM Cortex-M4 Microcontroller

兆易创新GD32F350CBT6-GD32 ARM Cortex-M4 Microcontroller GigaDevice Semiconductor Inc. GD32F350xx ARM® Cortex®-M4 32-bit MCU Datasheet General description The GD32F350xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support. The GD32F350xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five general 16-bit timers, a general 32-bit timer, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, an I2S, a HDMI-CEC, a TSI and an USBFS. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F350xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. Device information Table 2-1. GD32F350xx devices features and peripheral list   Part Number GD32F350xx   G4 G6 G8 K4 K6 K8 C4 C6 C8 CB R4 R6 R8 RB Flash Code area (KB)   16   32   64   16   32   64   16   32   64   64   16   32   64   64   Data area (KB)   0   0   0   0   0   0   0   0   0   64   0   0   0   64   Total (KB)   16   32   64   16   32   64   16   32   64   128   16   32   64   128 SRAM (KB) 4 6 8 4 6 8 4 6 8 16 4 8 16 16 Timers General timer (32-bit) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1)   General timer (16-bit) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16) 5 (2,13-16)   Advanced timer (16-bit) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0)   Basic timer (16-bit) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5) 1 (5)   SysTick
兆易创新GD32-GigaDevice-兆易创新代理
产品描述

兆易创新GD32F350CBT6-GD32 ARM Cortex-M4 Microcontroller

GigaDevice Semiconductor Inc.
GD32F350xx
ARM® Cortex®-M4 32-bit MCU
Datasheet

General description

The GD32F350xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost- performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support.
The GD32F350xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five general 16-bit timers, a general 32-bit timer, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, an I2S, a HDMI-CEC, a TSI and an USBFS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F350xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.

Device information

Table 2-1. GD32F350xx devices features and peripheral list

 

Part Number

GD32F350xx

 

G4

G6

G8

K4

K6

K8

C4

C6

C8

CB

R4

R6

R8

RB

Flash

Code area

(KB)

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

64

 

16

 

32

 

64

 

64

 

Data area

(KB)

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

64

 

0

 

0

 

0

 

64

 

Total

(KB)

 

16

 

32

 

64

 

16

 

32

 

64

 

16

 

32

 

64

 

128

 

16

 

32

 

64

 

128

SRAM (KB)

4

6

8

4

6

8

4

6

8

16

4

8

16

16

Timers

General timer

(32-bit)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

1

(1)

 

General timer

(16-bit)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

5

(2,13-16)

 

Advanced

timer (16-bit)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

1

(0)

 

Basic timer

(16-bit)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

1

(5)

 

SysTick

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Watchdog

2

2

2

2

2

2

2

2

2

2

2

2

2

2

 

RTC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Connectivity

 

USART

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

1

(0)

2

(0-1)

2

(0-1)

2

(0-1)

 

 

I2C

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

1

(0)

1

(0)

2

(0-1)

2

(0-1)

 

 

SPI/I2S

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

2/1

(0-1)/(0)

1/1

(0)/(0)

1/1

(0)/(0)

2/1

(0-1)/(0)

2/1

(0-1)/(0)

 

USBFS

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

HDMI-CEC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

GPIO

24

24

24

27

27

27

39

39

39

39

55

55

55

55

TSI

(Channels)

14

14

14

14

14

14

17

17

17

17

18

18

18

18

CMP

2

2

2

2

2

2

2

2

2

2

2

2

2

2

EXTI

16

16

16

16

16

16

16

16

16

16

16

16

16

16

 

 

Part Number

GD32F350xx

 

G4

G6

G8

K4

K6

K8

C4

C6

C8

CB

R4

R6

R8

RB

ADC

Units

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

Channels

(External)

10

10

10

10

10

10

10

10

10

10

16

16

16

16

 

Channels

(Internal)

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

 

3

DAC

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Package

QFN28

QFN32

LQFP48

LQFP64

 

Memory map

Table 2-2. GD32F350xx memory map

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0xE000 0000 - 0xE00F FFFF

Cortex-M4 internal peripherals

External Device

 

0xA000 0000 - 0xDFFF FFFF

Reserved

External RAM

 

0x6000 0000 - 0x9FFF FFFF

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripherals

 

AHB1

0x5004 0000 - 0x5FFF FFFF

Reserved

 

 

0x5000 0000 - 0x5003 FFFF

USBFS

 

 

 

 

 

AHB2

0x4800 1800 - 0x4FFF FFFF

Reserved

 

 

0x4800 1400 - 0x4800 17FF

GPIOF

 

 

0x4800 1000 - 0x4800 13FF

Reserved

 

 

0x4800 0C00 - 0x4800 0FFF

GPIOD

 

 

0x4800 0800 - 0x4800 0BFF

GPIOC

 

 

0x4800 0400 - 0x4800 07FF

GPIOB

 

 

0x4800 0000 - 0x4800 03FF

GPIOA

 

 

 

 

 

 

 

AHB1

0x4002 4400 - 0x47FF FFFF

Reserved

 

 

0x4002 4000 - 0x4002 43FF

TSI

 

 

0x4002 3400 - 0x4002 3FFF

Reserved

 

 

0x4002 3000 - 0x4002 33FF

CRC

 

 

0x4002 2400 - 0x4002 2FFF

Reserved

 

 

0x4002 2000 - 0x4002 23FF

FMC

 

 

0x4002 1400 - 0x4002 1FFF

Reserved

 

 

0x4002 1000 - 0x4002 13FF

RCU

 

 

0x4002 0400 - 0x4002 0FFF

Reserved

 

 

0x4002 0000 - 0x4002 03FF

DMA

 

 

 

 

 

 

 

 

 

 

APB2

0x4001 8000 - 0x4001 FFFF

Reserved

 

 

0x4001 5C00 - 0x4001 7FFF

Reserved

 

 

0x4001 4C00 - 0x4001 5BFF

Reserved

 

 

0x4001 4800 - 0x4001 4BFF

TIMER16

 

 

0x4001 4400 - 0x4001 47FF

TIMER15

 

 

0x4001 4000 - 0x4001 43FF

TIMER14

 

 

0x4001 3C00 - 0x4001 3FFF

Reserved

 

 

0x4001 3800 - 0x4001 3BFF

USART0

 

 

0x4001 3400 - 0x4001 37FF

Reserved

 

 

0x4001 3000 - 0x4001 33FF

SPI0/I2S0

 

 

0x4001 2C00 - 0x4001 2FFF

TIMER0

 

 

0x4001 2800 - 0x4001 2BFF

Reserved

 

 

0x4001 2400 - 0x4001 27FF

ADC

 

 

0x4001 0800 - 0x4001 23FF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x4001 0400 - 0x4001 07FF

EXTI

 

 

0x4001 0000 - 0x4001 03FF

SYSCFG + CMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

APB1

0x4000 CC00 - 0x4000 FFFF

Reserved

 

 

0x4000 C800 - 0x4000 CBFF

CTC

 

 

0x4000 C400 - 0x4000 C7FF

Reserved

 

 

0x4000 C000 - 0x4000 C3FF

Reserved

 

 

0x4000 8000 - 0x4000 BFFF

Reserved

 

 

0x4000 7C00 - 0x4000 7FFF

Reserved

 

 

0x4000 7800 - 0x4000 7BFF

CEC

 

 

0x4000 7400 - 0x4000 77FF

DAC

 

 

0x4000 7000 - 0x4000 73FF

PMU

 

 

0x4000 6400 - 0x4000 6FFF

Reserved

 

 

0x4000 6000 - 0x4000 63FF

Reserved

 

 

0x4000 5C00 - 0x4000 5FFF

Reserved

 

 

0x4000 5800 - 0x4000 5BFF

I2C1

 

 

0x4000 5400 - 0x4000 57FF

I2C0

 

 

0x4000 4800 - 0x4000 53FF

Reserved

 

 

0x4000 4400 - 0x4000 47FF

USART1

 

 

0x4000 4000 - 0x4000 43FF

Reserved

 

 

0x4000 3C00 - 0x4000 3FFF

Reserved

 

 

0x4000 3800 - 0x4000 3BFF

SPI1

 

 

0x4000 3400 - 0x4000 37FF

Reserved

 

 

0x4000 3000 - 0x4000 33FF

FWDGT

 

 

0x4000 2C00 - 0x4000 2FFF

WWDGT

 

 

0x4000 2800 - 0x4000 2BFF

RTC

 

 

0x4000 2400 - 0x4000 27FF

Reserved

 

 

0x4000 2000 - 0x4000 23FF

TIMER13

 

 

0x4000 1400 - 0x4000 1FFF

Reserved

 

 

0x4000 1000 - 0x4000 13FF

TIMER5

 

 

0x4000 0800 - 0x4000 0FFF

Reserved

 

 

0x4000 0400 - 0x4000 07FF

TIMER2

 

 

0x4000 0000 - 0x4000 03FF

TIMER1

 

SRAM

 

0x2000 4000 - 0x3FFF FFFF

Reserved

 

 

0x2000 0000 - 0x2000 3FFF

SRAM

 

 

 

Code

 

0x1FFF FC00 - 0x1FFF FFFF

Reserved

 

 

0x1FFF F800 - 0x1FFF FBFF

Option bytes

 

 

0x1FFF EC00 - 0x1FFF F7FF

System memory

 

 

0x0810 0000 - 0x1FFF EBFF

Reserved

 

 

0x0800 0000 - 0x0801 FFFF

Main Flash memory

 

 

0x0010 0000 - 0x07FF FFFF

Reserved

 

Pre-defined

Regions

 

Bus

 

Address

 

Peripherals

 

 

0x0000 0000 - 0x000F FFFF

Aliased to Flash or system memory

GD32F350Rx LQFP64 pin definitions

Table 2-3. GD32F350Rx LQFP64 pin definitions

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13- TAMPER-

RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

PF0-OSCIN

 

5

 

I/O

 

5VT

Default: PF0

Alternate: CTC_SYNC Additional: OSCIN

PF1- OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

 

PC0

 

8

 

I/O

 

Default: PC0

Alternate: EVENTOUT Additional: ADC_IN10

 

PC1

 

9

 

I/O

 

Default: PC1

Alternate: EVENTOUT Additional: ADC_IN11

 

PC2

 

10

 

I/O

 

Default: PC2 Alternate: EVENTOUT

Additional: ADC_IN12

 

PC3

 

11

 

I/O

 

Default: PC3 Alternate: EVENTOUT

Additional: ADC_IN13

VSSA

12

P

 

Default: VSSA

VDDA

13

P

 

Default: VDDA

 

 

 

PA0-WKUP

 

 

 

14

 

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL(5)

Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1,

WKUP0

 

 

PA1

 

 

15

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1, CMP0_IP

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PA2

 

 

 

 

Alternate: USART0_TX(3), USART1_TX(4),

PA2

16

I/O

 

TIMER1_CH2, TIMER14_CH0 ,

 

 

 

 

CMP1_OUT,TSI_G0_IO2

 

 

 

 

Additional: ADC_IN2, CMP1_IM6

 

 

 

 

Default: PA3

PA3

17

I/O

 

Alternate: USART0_RX(3), USART1_RX(4),

TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3

 

 

 

 

Additional: ADC_IN3, CMP1_IP

 

PF4

 

18

 

I/O

 

5VT

Default: PF4

Alternate: EVENTOUT

 

PF5

 

19

 

I/O

 

5VT

Default: PF5

Alternate: EVENTOUT

 

 

 

 

Default: PA4

 

 

 

 

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),

PA4

20

I/O

 

USART1_CK(4), TIMER13_CH0, TSI_G1_IO0,

SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4, CMP0_IM4, CMP1_IM4,

 

 

 

 

DAC0_OUT

 

 

 

 

Default: PA5

PA5

21

I/O

 

Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0,

TIMER1_ETI, TSI_G1_IO1

 

 

 

 

Additional: ADC_IN5, CMP0_IM5, CMP1_IM5

 

 

 

 

Default: PA6

 

 

 

 

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,

PA6

22

I/O

 

TIMER0_BKIN, TIMER15_CH0, CMP0_OUT,

 

 

 

 

TSI_G1_IO2, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,

PA7

23

I/O

 

TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,

 

 

 

 

CMP1_OUT, TSI_G1_IO3, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PC4

PC4

24

I/O

 

Alternate: EVENTOUT

 

 

 

 

Additional: ADC_IN14

 

 

 

 

Default: PC5

PC5

25

I/O

 

Alternate: TSI_G2_IO0

 

 

 

 

Additional: ADC_IN15, WKUP4

 

 

 

 

Default: PB0

PB0

26

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

TSI_G2_IO1, USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

27

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

 

 

 

 

TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK(5)

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Additional: ADC_IN9

 

PB2

 

28

 

I/O

 

5VT

Default: PB2

Alternate: TSI_G2_IO3

 

 

 

 

Default: PB10

PB10

29

I/O

5VT

Alternate: I2C0_SCL(3),I2C1_SCL(5), CEC,

 

 

 

 

TIMER1_CH2, TSITG, SPI1_IO2(5)

 

 

 

 

Default: PB11

PB11

30

I/O

5VT

Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3,

 

 

 

 

TSI_G5_IO0, EVENTOUT, SPI1_IO3(5)

VSS

31

P

 

Default: VSS

VDD

32

P

 

Default: VDD

 

 

 

 

Default: PB12

PB12

33

I/O

5VT

Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN,

 

 

 

 

TSI_G5_IO1, I2C1_SMBA(5), EVENTOUT

 

 

 

 

Default: PB13

PB13

34

I/O

5VT

Alternate: SPI0_SCK(3), SPI1_SCK(5),

 

 

 

 

TIMER0_CH0_ON, TSI_G5_IO2

 

 

 

 

Default: PB14

PB14

35

I/O

5VT

Alternate: SPI0_MISO(3), SPI1_MISO(5),

 

 

 

 

TIMER0_CH1_ON, TIMER14_CH0, TSI_G5_IO3

 

 

 

 

Default: PB15

 

 

 

 

Alternate: SPI0_MOSI(3), SPI1_MOSI(5),

PB15

36

I/O

5VT

TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

PC6

 

37

 

I/O

 

5VT

Default: PC6

Alternate: TIMER2_CH0, I2S0_MCK

 

PC7

 

38

 

I/O

 

5VT

Default: PC7

Alternate: TIMER2_CH1

 

PC8

 

39

 

I/O

 

5VT

Default: PC8

Alternate: TIMER2_CH2

 

PC9

 

40

 

I/O

 

5VT

Default: PC9

Alternate: TIMER2_CH3

 

 

 

 

Default: PA8

PA8

41

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,USBFS_SOF,CTC_SYNC

 

 

 

 

Default: PA9

PA9

42

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN,

 

 

 

 

TSI_G3_IO0, I2C0_SCL,USBFS_VBUS

 

 

 

 

Default: PA10

PA10

43

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

TSI_G3_IO1, I2C0_SDA, USBFS_ID

 

 

 

 

Default: PA11

PA11

44

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT,

TSI_G3_IO2, EVENTOUT, SPI1_IO2(5)

 

 

 

 

Additional: USBFS_DM

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PA12

PA12

45

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT,

TSI_G3_IO3, EVENTOUT, SPI1_IO3(5)

 

 

 

 

Additional: USBFS_DP

 

PA13

 

46

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PF6

 

47

 

I/O

 

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

 

PF7

 

48

 

I/O

 

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

 

 

 

 

Default: PA14

PA14

49

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

50

I/O

5VT

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

USART1_RX(4), TIMER1_CH0, TIMER1_ETI,

 

 

 

 

SPI1_NSS(5), EVENTOUT

PC10

51

I/O

5VT

Default: PC10

PC11

52

I/O

5VT

Default: PC11

PC12

53

I/O

5VT

Default: PC12

 

PD2

 

54

 

I/O

 

5VT

Default: PD2

Alternate: TIMER2_ETI

 

 

 

 

Default: PB3

PB3

55

I/O

5VT

Alternate: SPI0_SCK, I2S0_CK, TIMER1_CH1,

 

 

 

 

TSI_G4_IO0, EVENTOUT

 

 

 

 

Default: PB4

PB4

56

I/O

5VT

Alternate: SPI0_MISO,I2S0_MCK, TIMER2_CH0,

 

 

 

 

TSI_G4_IO1, EVENTOUT

 

 

 

 

Default: PB5

PB5

57

I/O

5VT

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA,

TIMER15_BKIN, TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

 

 

 

Default: PB6

PB6

58

I/O

5VT

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON,

 

 

 

 

TSI_G4_IO2

 

 

 

 

Default: PB7

PB7

59

I/O

5VT

Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,T

 

 

 

 

SI_G4_IO3

BOOT0

60

I

 

Default: BOOT0

 

PB8

 

61

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG

 

 

 

 

Default: PB9

PB9

62

I/O

5VT

Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,

 

 

 

 

EVENTOUT, I2S0_MCK

VSS

63

P

 

Default: VSS

 

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

VDD

64

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F350R4 devices only.
(4)Functions are available on GD32F350RB/8/6 devices.
(5)Functions are available on GD32F350RB/8 devices.

GD32F350Cx LQFP48 pin definitions

Table 2-4. GD32F350Cx LQFP48 pin definitions

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

VBAT

1

P

 

Default: VBAT

PC13- TAMPER-

RTC

 

2

 

I/O

 

 

Default: PC13

Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1

PC14- OSC32IN

 

3

 

I/O

 

Default: PC14 Additional: OSC32IN

PC15-

OSC32OUT

 

4

 

I/O

 

Default: PC15 Additional: OSC32OUT

 

PF0-OSCIN

 

5

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1-

OSCOUT

 

6

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

7

I/O

 

Default: NRST

VSSA

8

P

 

Default: VSSA

VDDA

9

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

10

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL(5)

Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1, WKUP0

 

 

PA1

 

 

11

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1, CMP0_IP

 

 

PA2

 

 

12

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 , CMP1_OUT,TSI_G0_IO2

Additional: ADC_IN2, CMP1_IM6

PA3

13

I/O

 

Default: PA3

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: USART0_RX(3), USART1_RX(4),

 

 

 

 

TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3

 

 

 

 

Additional: ADC_IN3, CMP1_IP

 

 

 

 

Default: PA4

 

 

 

 

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),

PA4

14

I/O

 

USART1_CK(4), TIMER13_CH0, TSI_G1_IO0,

SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4, CMP0_IM4, CMP1_IM4,

 

 

 

 

DAC0_OUT

 

 

 

 

Default: PA5

PA5

15

I/O

 

Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0,

TIMER1_ETI, TSI_G1_IO1

 

 

 

 

Additional: ADC_IN5, CMP0_IM5, CMP1_IM5

 

 

 

 

Default: PA6

 

 

 

 

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,

PA6

16

I/O

 

TIMER0_BKIN, TIMER15_CH0, CMP0_OUT,

 

 

 

 

TSI_G1_IO2, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,

PA7

17

I/O

 

TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,

 

 

 

 

CMP1_OUT, TSI_G1_IO3, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

18

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

TSI_G2_IO1, USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

19

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

 

PB2

 

20

 

I/O

 

5VT

Default: PB2

Alternate: TSI_G2_IO3

 

 

 

 

Default: PB10

PB10

21

I/O

5VT

Alternate: I2C0_SCL(3),I2C1_SCL(5), CEC, TIMER1_CH2,

 

 

 

 

TSITG, SPI1_IO2(5)

 

 

 

 

Default: PB11

PB11

22

I/O

5VT

Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3,

 

 

 

 

TSI_G5_IO0, EVENTOUT, SPI1_IO3(5)

VSS

23

P

 

Default: VSS

VDD

24

P

 

Default: VDD

 

 

 

 

Default: PB12

PB12

25

I/O

5VT

Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN,

 

 

 

 

TSI_G5_IO1, I2C1_SMBA(5), EVENTOUT

PB13

26

I/O

5VT

Default: PB13

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON,

 

 

 

 

TSI_G5_IO2

 

 

 

 

Default: PB14

PB14

27

I/O

5VT

Alternate: SPI0_MISO(3), SPI1_MISO(5),

 

 

 

 

TIMER0_CH1_ON, TIMER14_CH0, TSI_G5_IO3

 

 

 

 

Default: PB15

 

PB15

 

28

 

I/O

 

5VT

Alternate: SPI0_MOSI(3), SPI1_MOSI(5),

TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1

 

 

 

 

Additional: RTC_REFIN, WKUP6

 

 

 

 

Default: PA8

PA8

29

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,USBFS_SOF,CTC_SYNC

 

 

 

 

Default: PA9

PA9

30

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN,

 

 

 

 

TSI_G3_IO0, I2C0_SCL,USBFS_VBUS

 

 

 

 

Default: PA10

PA10

31

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

TSI_G3_IO1, I2C0_SDA, USBFS_ID

 

 

 

 

Default: PA11

PA11

32

I/O

5VT

Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT,

TSI_G3_IO2, EVENTOUT, SPI1_IO2(5)

 

 

 

 

Additional: USBFS_DM

 

 

 

 

Default: PA12

PA12

33

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT,

TSI_G3_IO3, EVENTOUT, SPI1_IO3(5)

 

 

 

 

Additional: USBFS_DP

 

PA13

 

34

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

PF6

 

35

 

I/O

 

5VT

Default: PF6

Alternate: I2C0_SCL(3), I2C1_SCL(5)

 

PF7

 

36

 

I/O

 

5VT

Default: PF7

Alternate: I2C0_SDA(3), I2C1_SDA(5)

 

 

 

 

Default: PA14

PA14

37

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

38

I/O

5VT

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

USART1_RX(4), TIMER1_CH0, TIMER1_ETI,

 

 

 

 

SPI1_NSS(5), EVENTOUT

 

 

 

 

Default: PB5

PB5

41

I/O

5VT

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA,

TIMER15_BKIN, TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

PB6

 

42

 

I/O

 

5VT

Default: PB6

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON,

 

 

Pin Name

 

Pins

Pin Type(1)

I/O Level(2)

 

Functions description

 

 

 

 

TSI_G4_IO2

 

PB7

 

43

 

I/O

 

5VT

Default: PB7 Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,T

SI_G4_IO3

BOOT0

44

I

 

Default: BOOT0

 

PB8

 

45

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG

 

PB9

 

46

 

I/O

 

5VT

Default: PB9

Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,

EVENTOUT, I2S0_MCK

VSS

47

P

 

Default: VSS

VDD

48

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F350C4 devices only.
(4)Functions are available on GD32F350CB/8/6 devices.
(5)Functions are available on GD32F350CB/8 devices.

GD32F350Kx QFN32 pin definitions

Table 2-5. GD32F350Kx QFN32 pin definitions

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

PF0-OSCIN

 

2

 

I/O

 

5VT

Default: PF0 Alternate: CTC_SYNC

Additional: OSCIN

PF1-

OSCOUT

 

3

 

I/O

 

5VT

Default: PF1 Additional: OSCOUT

NRST

4

I/O

 

Default: NRST

VDDA

5

P

 

Default: VDDA

 

 

PA0-WKUP

 

 

6

 

 

I/O

 

Default: PA0

Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL(5)

Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1, WKUP0

 

 

PA1

 

 

7

 

 

I/O

 

Default: PA1

Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA(5), EVENTOUT

Additional: ADC_IN1, CMP0_IP

 

 

PA2

 

 

8

 

 

I/O

 

Default: PA2

Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 , CMP1_OUT,TSI_G0_IO2

Additional: ADC_IN2, CMP1_IM6

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

Default: PA3

PA3

9

I/O

 

Alternate: USART0_RX(3), USART1_RX(4),

TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3

 

 

 

 

Additional: ADC_IN3, CMP1_IP

 

 

 

 

Default: PA4

 

 

 

 

Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),

PA4

10

I/O

 

USART1_CK(4), TIMER13_CH0, TSI_G1_IO0,

SPI1_NSS(5)

 

 

 

 

Additional: ADC_IN4, CMP0_IM4, CMP1_IM4,

 

 

 

 

DAC0_OUT

 

 

 

 

Default: PA5

PA5

11

I/O

 

Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0,

TIMER1_ETI, TSI_G1_IO1

 

 

 

 

Additional: ADC_IN5, CMP0_IM5, CMP1_IM5

 

 

 

 

Default: PA6

 

 

 

 

Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,

PA6

12

I/O

 

TIMER0_BKIN, TIMER15_CH0, CMP0_OUT,

 

 

 

 

TSI_G1_IO2, EVENTOUT

 

 

 

 

Additional: ADC_IN6

 

 

 

 

Default: PA7

 

 

 

 

Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,

PA7

13

I/O

 

TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,

 

 

 

 

CMP1_OUT, TSI_G1_IO3, EVENTOUT

 

 

 

 

Additional: ADC_IN7

 

 

 

 

Default: PB0

PB0

14

I/O

 

Alternate: TIMER2_CH2, TIMER0_CH1_ON,

TSI_G2_IO1, USART1_RX(4), EVENTOUT

 

 

 

 

Additional: ADC_IN8

 

 

 

 

Default: PB1

PB1

15

I/O

 

Alternate: TIMER2_CH3, TIMER13_CH0,

TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK(5)

 

 

 

 

Additional: ADC_IN9

 

PB2

 

16

 

I/O

 

5VT

Default: PB2

Alternate: TSI_G2_IO3

VDD

17

P

 

Default: VDD

 

 

 

 

Default: PA8

PA8

18

I/O

5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT,

 

 

 

 

USART1_TX(4), EVENTOUT,USBFS_SOF,CTC_SYNC

 

 

 

 

Default: PA9

PA9

19

I/O

5VT

Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN,

 

 

 

 

TSI_G3_IO0, I2C0_SCL,USBFS_VBUS

 

 

 

 

Default: PA10

PA10

20

I/O

5VT

Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,

 

 

 

 

TSI_G3_IO1, I2C0_SDA, USBFS_ID

 

PA11

 

21

 

I/O

 

5VT

Default: PA11

Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT,

 

 

Pin Name

 

Pins

Pin

Type(1)

I/O

Level(2)

 

Functions description

 

 

 

 

TSI_G3_IO2, EVENTOUT, SPI1_IO2(5)

 

 

 

 

Additional: USBFS_DM

 

 

 

 

Default: PA12

PA12

22

I/O

5VT

Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT,

TSI_G3_IO3, EVENTOUT, SPI1_IO3(5)

 

 

 

 

Additional: USBFS_DP

 

PA13

 

23

 

I/O

 

5VT

Default: PA13

Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)

 

 

 

 

Default: PA14

PA14

24

I/O

5VT

Alternate: USART0_TX(3), USART1_TX(4), SWCLK,

 

 

 

 

SPI1_MOSI(5)

 

 

 

 

Default: PA15

PA15

25

I/O

5VT

Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3),

USART1_RX(4), TIMER1_CH0, TIMER1_ETI,

 

 

 

 

SPI1_NSS(5), EVENTOUT

 

 

 

 

Default: PB3

PB3

26

I/O

5VT

Alternate: SPI0_SCK, I2S0_CK, TIMER1_CH1,

 

 

 

 

TSI_G4_IO0, EVENTOUT

 

 

 

 

Default: PB4

PB4

27

I/O

5VT

Alternate: SPI0_MISO,I2S0_MCK, TIMER2_CH0,

 

 

 

 

TSI_G4_IO1, EVENTOUT

 

 

 

 

Default: PB5

PB5

28

I/O

5VT

Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA,

TIMER15_BKIN, TIMER2_CH1

 

 

 

 

Additional:WKUP5

 

 

 

 

Default: PB6

PB6

29

I/O

5VT

Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON,

 

 

 

 

TSI_G4_IO2

 

 

 

 

Default: PB7

PB7

30

I/O

5VT

Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,T

 

 

 

 

SI_G4_IO3

BOOT0

31

I

 

Default: BOOT0

 

PB8

 

32

 

I/O

 

5VT

Default: PB8

Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG

VDD

1

P

 

Default: VDD

Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available on GD32F350K4 devices only.
(4)Functions are available on GD32F350K8/6 devices.
(5)Functions are available on GD32F350K8 devices.

ARM® Cortex®-M4 core

The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer

The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)


On-chip memory

Up to 128 Kbytes of Flash memory
Up to 16 Kbytes of SRAM with hardware parity checking

The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash and 16 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. Table 2-2. GD32F350xx memory map shows the memory map of the GD32F350xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.

3.3Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 108 MHz/54 MHz/54 MHz. See Figure 2-6. GD32F350xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present.

Boot modes

At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15).

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, CMP0/CMP1 output, LVD output, USART wakeup, CEC wakeup and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin.

Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.86 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor

One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage (VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx)

and the advanced timer (TIMER0) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

Digital to analog converter (DAC)

12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+.

DMA

7 channel DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC and I2S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.

General-purpose inputs/outputs (GPIOs)

Up to 55 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable

There are up to 55 general purpose I/O pins (GPIO) in GD32F350xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push- pull open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.

All GPIOs are high-current capable except for analog inputs.


Timers and PWM generation

One 16-bit advanced timer (TIMER0), one 32-bit general timer (TIMER1), five 16-bit general timers (TIMER2, TIMER13 ~ TIMER16), and one 16-bit basic timer (TIMER5)
Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)

The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5, is mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F350xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode.

The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source


Real time clock (RTC)

Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month
automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler.

Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

Serial peripheral interface (SPI)

Up to two SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter (USART)
Up to two USARTs with operating frequency up to 6.75 MB/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface

The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication.

Inter-IC sound (I2S)

One I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI0
Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F350xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI0. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error.

HDMI CEC

Hardware support Consumer Electronics Control (CEC) protocol (HDMI standard rev1.4)

The CEC protocol provides high-level control functions between the audiovisual products linked with HDMI cables. GD32F350xx contain a HDMI-CEC controller which has an independent clock domain and can wake up the MCU from deep-sleep mode on data reception.

Universal serial bus full-speed interface (USBFS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator (IRC48M) support crystal-less operation
Internal main PLL for USB CLK compliantly
Internal USBFS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) or by the internal 48 MHz oscillator (IRC48M) in automatic trimming mode that allows crystal-less operation.

Touch sensing interface (TSI)

Charge transfer sequence fully controlled by hardware
6 fully parallel groups implemented
18 IOs configurable for capacitive sensing Channel Pins and 6 for Sample Pins
Configurable transfer sequence frequency
Able to implement the user specific charge transfer sequences
Sequence end and error flags / configurable interrupts
Spread spectrum function implemented

Capacitive sensing technology can be used for the detection of a finger (or any conductive object) presence near an electrode. The capacitive variation of the electrode introduced by the finger can be measured by charging and detecting the voltage across the sampling capacitor. GD32F350xx contain a hardware touch sensing interface (TSI) and only requires few external components to operate. The sensing channels are distributed over 6 analog I/O groups including: Group0 (PA0 ~ PA3), Group1 (PA4 ~ PA7), Group2 (PC5, PB0 ~ PB2),

Group3 (PA9 ~ PA12), Group4 (PB3, PB4, PB6, PB7) and Group5 (PB11 ~ PB14),


Comparators (CMP)

Two fast rail-to-rail low-power comparators with software configurable
Programmable reference voltage (internal, external I/O or DAC output pin)

Two Comparators (CMP) are implemented within the devices. Both comparators can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.

Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Package and operation temperature

LQFP64 (GD32F350Rx), LQFP48 (GD32F350Cx), QFN32 (GD32F350Kx) and QFN28 (GD32F350Gx)
Operation temperature range: -40°C to +85°C (industrial level)

扫二维码用手机看

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗

uA级别智能门锁低功耗雷达模块让门锁更加智能省电节约功耗,指纹门锁并不是什么新鲜事,我相信每个人都很熟悉。随着近年来智能家居的逐步普及,指纹门锁也进入了成千上万的家庭。今天的功耗雷达模块指纹门锁不仅消除了繁琐的钥匙,而且还提供了各种智能功能,uA级别智能门锁低功耗雷达模块用在智能门锁上,可以实现门锁的智能感应屏幕,使电池寿命延长3-5倍,如与其他智能家居连接,成为智能场景的开关。所以今天的指纹门锁更被称为智能门锁。 今天,让我们来谈谈功耗雷达模块智能门锁的安全性。希望能让更多想知道智能门锁的朋友认识下。 指纹识别是智能门锁的核心 指纹识别技术在我们的智能手机上随处可见。从以前的实体指纹识别到屏幕下的指纹识别,可以说指纹识别技术已经相当成熟。指纹识别可以说是整个uA级低功耗雷达模块智能门锁的核心。 目前主要有三种常见的指纹识别方法,即光学指纹识别、半导体指纹识别和超声指纹识别。 光学指纹识别 让我们先谈谈光学指纹识别的原理实际上是光的反射。我们都知道指纹本身是不均匀的。当光照射到我们的指纹上时,它会反射,光接收器可以通过接收反射的光来绘制我们的指纹。就像激光雷达测绘一样。 光学指纹识别通常出现在打卡机上,手机上的屏幕指纹识别技术也使用光学指纹识别。今天的光学指纹识别已经达到了非常快的识别速度。 然而,光学指纹识别有一个缺点,即硬件上的活体识别无法实现,容易被指模破解。通常,活体识别是通过软件算法进行的。如果算法处理不当,很容易翻车。 此外,光学指纹识别也容易受到液体的影响,湿手解锁的成功率也会下降。 超声指纹识别 超声指纹识别也被称为射频指纹识别,其原理与光学类型相似,但超声波使用声波反射,实际上是声纳的缩小版本。因为使用声波,不要担心水折射会降低识别率,所以超声指纹识别可以湿手解锁。然而,超声指纹识别在防破解方面与光学类型一样,不能实现硬件,可以被指模破解,活体识别仍然依赖于算法。 半导体指纹识别 半导体指纹识别主要采用电容、电场(即我们所说的电感)、温度和压力原理来实现指纹图像的收集。当用户将手指放在前面时,皮肤形成电容阵列的极板,电容阵列的背面是绝缘极板。由于不同区域指纹的脊柱与谷物之间的距离也不同,因此每个单元的电容量随之变化,从而获得指纹图像。半导体指纹识别具有价格低、体积小、识别率高的优点,因此大多数uA级低功耗雷达模块智能门锁都采用了这种方案。半导体指纹识别的另一个功能是活体识别。传统的硅胶指模无法破解。 当然,这并不意味着半导体可以百分识别活体。所谓的半导体指纹识别活体检测不使用指纹活体体征。本质上,它取决于皮肤的材料特性,这意味着虽然传统的硅胶指模无法破解。 一般来说,无论哪种指纹识别,都有可能被破解,只是说破解的水平。然而,今天的指纹识别,无论是硬件生活识别还是算法生活识别,都相对成熟,很难破解。毕竟,都可以通过支付级别的认证,大大保证安全。 目前,市场上大多数智能门锁仍将保留钥匙孔。除了指纹解锁外,用户还可以用传统钥匙开门。留下钥匙孔的主要目的是在指纹识别故障或智能门锁耗尽时仍有开门的方法。但由于有钥匙孔,它表明它可以通过技术手段解锁。 目前市场上的锁等级可分为A、B、C三个等级,这三个等级主要是通过防暴开锁和防技术开锁的程度来区分的。A级锁要求技术解锁时间不少于1分钟,B级锁要求不少于5分钟。即使是高级别的C级锁也只要求技术解锁时间不少于10分钟。 也就是说,现在市场上大多数门锁,无论是什么级别,在专业的解锁大师面前都糊,只不过是时间长短。 安全是重要的,是否安全增加了人们对uA级别低功耗雷达模块智能门锁安全的担忧。事实上,现在到处都是摄像头,强大的人脸识别,以及移动支付的出现,使家庭现金减少,所有这些都使得入室盗窃的成本急剧上升,近年来各省市的入室盗窃几乎呈悬崖状下降。 换句话说,无论锁有多安全,无论锁有多难打开,都可能比在门口安装摄像头更具威慑力。 因此,担心uA级别低功耗雷达模块智能门锁是否不安全可能意义不大。毕竟,家里的防盗锁可能不安全。我们应该更加关注门锁能给我们带来多少便利。 我们要考虑的是智能门锁的兼容性和通用性。毕竟,智能门锁近年来才流行起来。大多数人在后期将普通机械门锁升级为智能门锁。因此,智能门锁能否与原门兼容是非常重要的。如果不兼容,发现无法安装是一件非常麻烦的事情。 uA级别低功耗雷达模块智能门锁主要是为了避免带钥匙的麻烦。因此,智能门锁的便利性尤为重要。便利性主要体现在指纹的识别率上。手指受伤导致指纹磨损或老年人指纹较浅。智能门锁能否识别是非常重要的。 当然,如果指纹真的失效,是否有其他解锁方案,如密码解锁或NFC解锁。还需要注意密码解锁是否有虚假密码等防窥镜措施。 当然,智能门锁的耐久性也是一个需要特别注意的地方。uA级别低功耗雷达模块智能门锁主要依靠内部电池供电,这就要求智能门锁的耐久性尽可能好,否则经常充电或更换电池会非常麻烦。
点击查看更多
14
2022-01

微波雷达传感器雷达感应浴室镜上的应用

发布时间: : 2022-01--14
微波雷达传感器雷达感应浴室镜上的应用,如今,家用电器的智能化已成为一种常态,越来越多的人开始在自己的浴室里安装智能浴室镜。但是还有很多人对智能浴镜的理解还不够深入,今天就来说说这个话题。 什么是智能浴室镜?智慧型浴室镜,顾名思义,就是卫浴镜子智能化升级,入门级产品基本具备了彩灯和镜面触摸功能,更高档次的产品安装有微波雷达传感器智能感应,当感应到有人接近到一定距离即可开启亮灯或者亮屏操作,也可三色无极调,智能除雾,语音交互,日程安排备忘,甚至在镜子上看电视,听音乐,气象预报,问题查询,智能控制,健康管理等。 智能化雷达感应浴室镜与普通镜的区别,为什么要选TA?,就功能而言,普通浴镜价格用它没有什么压力!而且雷达感应智能浴镜会让人犹豫不决是否“值得一看”。就功能和应用而言,普通浴镜功能单一,而微波雷达传感器智能浴室镜功能创新:镜子灯光色温和亮度可以自由调节,镜面还可以湿手触控,智能除雾,既环保又健康! 尽管智能浴镜比较新颖,但功能丰富,体验感更好,特别是入门级的智能浴镜,具有基础智能化功能,真的适合想体验下智能化的小伙伴们。 给卫生间安装微波雷达传感器浴室镜安装注意什么? ①确定智能浴室镜的安装位置,因为是安装时在墙壁上打孔,一旦安装后一般无法移动位置。 ②在选购雷达感应智能浴室镜时,根据安装位置确定镜子的形状和尺寸。 ③确定智能浴镜的安装位置后,在布线时为镜子预留好电源线。 ④确定微波雷达传感器智能浴镜的安装高度,一般智能浴镜的标准安装高度约85cm(从地砖到镜子底),具体安装高度要根据家庭成员的身高及使用习惯来决定。 ⑤镜面遇到污渍,可用酒精或30%清洁稀释液擦洗,平时可用干毛巾养护,注意多通风。
查看详情 查看详情
07
2022-02

冰箱屏幕唤醒微波雷达传感器屏幕唤醒性能强悍智能感应

发布时间: : 2022-02--07
冰箱屏幕唤醒微波雷达传感器屏幕唤醒性能强悍智能感应,随着年轻一代消费观念的转变,冰箱作为厨房和客厅的核心家用电器之一,也升级为健康、智能、高端的形象。在新产品发布会上,推出了大屏幕的冰箱,不仅屏幕优秀,而且微波雷达传感器屏幕唤醒性能强大。 大屏智能互联,听歌看剧购物新体验 冰箱植入冰箱屏幕唤醒微波雷达传感器触摸屏,重新定义了冰箱的核心价值。除了冰箱的保鲜功能外,该显示屏还集控制中心、娱乐中心和购物中心于一体,让您在无聊的烹饪过程中不会落后于听歌、看剧和购物。新的烹饪体验是前所未有的。 不仅如此,21.5英寸的屏幕也是整个房子智能互联的互动入口。未来的家将是一个充满屏幕的家。冰箱可以通过微波雷达传感器屏幕与家庭智能产品连接。烹饪时,你可以通过冰箱观看洗衣机的工作,当你不能腾出手来照顾孩子时,你可以通过冰箱屏幕连接家庭摄像头,看到孩子的情况。冰箱的推出标志着屏幕上的未来之家正在迅速到来。 管理RFID食材,建立健康的家庭生活 据报道,5G冰箱配备了RFID食品材料管理模块,用户将自动记录和储存食品,无需操作。此外,冰箱还可以追溯食品来源,监控食品材料从诞生到用户的整个过程,以确保食品安全;当食品即将过期时,冰箱会自动提醒用户提供健康的饮食和生活。 风冷无霜,清新无痕 冰箱的出现是人类延长食品保存期的一项伟大发明。一个好的冰箱必须有很强的保存能力。5g冰箱采用双360度循环供气系统。智能补水功能使食品原料享受全方位保鲜,紧紧锁住水分和营养,防止食品原料越来越干燥。此外,该送风系统可将其送到冰箱的每个角落,消除每个储藏空间的温差,减少手工除霜的麻烦,使食品不再粘连。 进口电诱导保鲜技术,创新黑科技加持 针对传统冰箱保存日期不够长的痛点,5g互联网冰箱采用日本进口电诱导保存技术,不仅可以实现水果储存冰箱2周以上不腐烂发霉,还可以使蔬菜储存25天不发黄、不起皱。在-1℃~-5℃下,配料不易冻结,储存时间较长。冷冻食品解冻后无血,营养大化。此外,微波雷达传感器5g冰箱还支持-7℃~-24℃的温度调节,以满足不同配料的储存要求。 180°矢量变频,省电时更安静 一台好的压缩机对冰箱至关重要。冰箱配备了变频压缩机。180°矢量变频技术可根据冷藏室和冷冻室的需要有效提供冷却,达到食品原料的保鲜效果。180°矢量变频技术不仅大大降低了功耗,而且以非常低的分贝操作机器。保鲜效果和节能安静的技术冰箱可以在许多智能冰箱中占有一席之地,仅仅通过这种搭配就吸引了许多消费者的青睐。 配备天然草本滤芯,不再担心串味 各种成分一起储存在冰箱中,难以避免串味。此外,冰箱内容易滋生细菌,冰箱总是有异味。针对这一问题,冰箱创新配置了天然草本杀菌除臭滤芯。该滤芯提取了多种天然草本活性因子,可有效杀菌99.9%,抑制冰箱异味,保持食材新鲜。不仅如此,这个草本滤芯可以更快、更方便、更无忧地拆卸。家里有冰箱,开始健康保鲜的生活。 目前,冰箱屏幕唤醒微波雷达传感器正在继续推动家庭物联网的快速普及,相信在不久的将来,智能家电将成为互动终端。
查看详情 查看详情
31
2023-01

上海乐鑫科技官网ESP32 ble wifi模块数据安全性揭秘

发布时间: : 2023-01--31
上海乐鑫科技官网ESP32 ble wifi模块数据安全性揭秘,众所周知,TCP 协议和 UDP 协议,及其之上的应用协议 HTTP 和 COAP,都是明文传输数据的,这样就会导致数据在网络传输的过程中被窃取或者篡改。如果数据中含有密码、账号等敏感信息,则可能会造成不可挽回的损失,因此需要对这些明文传输的数据进行加密。对于使用蓝牙传输的数据,由于蓝牙协议属于点对点的协议,数据不会泄露到网络上,被窃取的概率也很小;另外,上海乐鑫科技官网ESP32 ble wifi模块蓝牙协议本身也会对用户的数据进行加密。因此,本文主要讨论 TCP IP协议的数据加密。 加密是为了保证传输数据的机密性与完整性。常见的加密系统通常先对数据进行编码再传输例如,在以前的战争中,发送的电报就是经过编码的,接收方和发送方都有一个相同的密码本,接收方用密码本上的数字或者字母来替换电报中的单词、语句。即使电报内容被第三窃听了,第三方也无法在短时间破译出电报的真实内容。但是这种方式有个缺陷,就是电报的内容还是存在被破解的可能,只是时间的问题,而且为了防止电报被破解,接收方与发送方需要定期更换密码本,这时也有可能泄露密码本,导致电报内容被破解。 上述的电报例子就是常见的加密算法——对称加密的使用场景。在对称加密算法中,加密与解密采用的算法是一样的,它们的密钥也都是一样的。对称加密具有算法公开、计算量小、加密速度快、加密效率高等优点。但在数据传输前,发送方和接收方必须商定好密钥,而目为了保证数据不被破解,双方还必须定期更新密钥,这会使得密钥管理成为双方的负担。常用的对称加密算法有 AES、DES、RC4 等。 接下来介绍与对称加密相对的算法——非对称加密。上海乐鑫科技官网ESP32 ble wifi模块非对称加密的双方都有一对公开密钥(Public Key,公钥)与私有密钥 (Private Key,私钥),数据的加密使用公钥进行,数据的解密使用私钥进行。因为加密和解密使用的是两个不同的密钥,所以这种加密算法称为非对称加密。相比于对称加密,非对称加密更加安全。因为非对称加密比对称加密更复杂,所以在解密时会比对称加密慢,而且第三方很难直接破译数据。因为非对称加密算法的复杂度很高,并且用于解密的私钥是不会在网络中传播的,只有接收方才能获取到私钥,所以大大提高了数据的安全性。常见的非对称加密算法有 RSA、Diffe-Hellman、DSA等。 上海乐鑫科技官网ESP32 ble wifi模块非对称加密的优点是其安全性,用户 A 可以保留私钥,通过网络将公传输给用户 B,即使用户C获取了公钥,因为用户 C 没有用户A 的私钥,用户C 也是无法破解数据内容的。这样用户A 和用户B 就可以大胆地通过网络传输各自的公钥。记住一点,公钥是用于加密的,私钥是用于解密的。 非对称加密看起来似乎很安全,但是有没有想过这样一个问题: 如果用户C 将发往用户A 和用户 B 的公钥全部替换为自己对应私钥的公呢?用户 A 是不知道这个公是不是用户 B的,所以当用户A 发送数据时,就会使用用户 C 的公钥进行加密,这时用户 C 就可以在窃取该密文数据后使用对应的私钥进行解密。因此,如何保证公钥的合法性是至关重要的。在现实中,通过 CA (Certificate Authority) 可以保证公的合法性。CA 也是基于非对称加密算法来工作的,有了 CA,用户 B 会先把自己的公钥和一些其他信息交给 CA,CA 用自己的私钥加密这些数据,加密完的数据称为用户 B 的数字证书。用户 B 向用户A 传输的公是CA加密之后的数字证书。用户A 收到数宁证书后,会通过 CA 发布的数字证书 (包含了 CA的公钥)来解密用户B的数字证书,从而获得用户B 的公钥。
查看详情 查看详情
30
2023-01

乐鑫科技ESP32-C3蓝牙WiFi模块数据通信协议总结TCP/UDP/HTTP/CoAP协议

发布时间: : 2023-01--30
乐鑫科技ESP32-C3蓝牙WiFi模块数据通信协议总结TCP/UDP/HTTP/CoAP协议 乐鑫科技ESP32-C3蓝牙WiFi模块TCP 协议 可靠传输,支持重传、流量控制和拥塞控制; 面向连接,通过 3 次握手建立连接和 4 次握手断开连接,长连接; 一对一连接; 包头小为 20 B; 根据网络环境,在出现丢包时会重传,导致传输速率降低; 适用于可靠传输的应用,如文件传输等; 乐鑫科技ESP32-C3蓝牙WiFi模块UDP 协议 不可靠传输,不支持重传、流量控制和拥塞控制; 无连接,直接进行数据传输,短连接; 支持一对一单播,一对所有的广播和一对多的组播; 包头只有8B; 快,不受网络环境影响,只负责将数据传输到网络; 适用于实时传输应用,如 VoIP 电话、视频电话、流媒体等; 对于本地控制的数据通信而言,单纯从传输层的角度来讲,可选择 TCP 协议,因为需要数据的准确性;在使用 UDP 协议时,智能手机 App 会发送开灯命令,可能该命令由于网络环境问题被丢弃了,ESP32-C3 可能就无法收到该命令;相比于 TCP 协议而言,就算数据包被丢弃了,智能手机 App 底层还会重新发送该命令。 但使用单纯的传输层协议发送数据有个缺陷,需要用户自行开发上层应用业务逻辑,所以本节又介绍了基于 TCP和UDP 协议的应用协议 HTTP 和 COAP。 HTTP和CoAP 都是基于 REST 模型的网络传输协议,用于发送请求与响应请求,只是它们-个基于 TCP 协议,另一个基于 UDP 协议,并且各自继承了传输层协议的相关特性。HTTP 协议和 CoAP 协议的区别如下表所示。 乐鑫科技ESP32-C3蓝牙WiFi模块HTTP 协议 传输层TCP 协议; 可能含有大量消息头数据,开销大; 长连接,功耗高; 资源发现不支持; 一般由客户端主动触发,服务器端无法主动触发; 适用于性能好、内存比较多的设备; 乐鑫科技ESP32-C3蓝牙WiFi模块CoAP 协议 传输层UDP 协议; 包头采用二进制压缩,开销小; 短连接,功耗低; 资源发现支持; 虽然也有客户端与服务器端之分,但两者都可以主动触发; 适用于性能差、内存比较少的设备; 相比较而言,CoAP 协议更适合一些资源少的物联网设备,如果设备资源多、性能好,HTTP协议的功能比 CoAP 协议更加健全。对比了 TCP/IP 协议族内的通信协议后,接下来比较该类协议与蓝牙协议,它们直观的区别就是,蓝牙是点对点的协议,而 TCP/IP 协议是端对端的协议,中间可能会经过路由。因此在速度响应方面,同样是 2.4 GHZ 频道的无线传输技术,智能手机到 ESP32-C3 之间的数据通信上,蓝牙要快于 Wi-Fi。乐鑫科技ESP32-C3蓝牙WiFi模块蓝牙的数据包大小会比使用TCP/IP 协议栈的应用数据更小;蓝牙的功耗天然地比 Wi-Fi 功耗低。蓝牙协议支持资源发现,也不需要本地发现,因为蓝牙是点对点的连接,可以说蓝牙非常适合用于本地控制。但由于目前大部分物联网产品都要连云所以 Wi-Fi功能是必不可少的。很多物联网产品都可以只使用 Wi-Fi或者只使用蓝牙进行配网如果物联网产品不需要连云,则可以只使用蓝牙进行本地控制;如果物联网产品需要连云,则需要借助 Wi-Fi连云和进行本地控制。
查看详情 查看详情
29
2023-01

飞睿科技代理商乐鑫WiFi6 Soc ESP32-C6现货ESP-IDF v5.0发布

发布时间: : 2023-01--29
飞睿科技代理商乐鑫WiFi6 Soc ESP32-C6现货ESP-IDF v5.0发布,ESP32-C6是乐鑫科技的支持WiFi6的SoC,集成2.4GHz Wi-Fi6、Bluetooth5(LE)和IEEE802.15.4协议(Thread/Zigbee)。目前,ESP32-C6已上架销售,可到飞睿科技官方淘宝店购买。 飞睿科技代理商乐鑫ESP32-C6 一个时钟频率高达1600MHz的高性能RISC-V32位处理器,一个时钟频率高20位MHz的低功耗RISC-V内置512位处理器的32位处理器KBSRAM,320KBROM,并支持外接flash。ESP32-C6拥有30个(QFN40)或22个(QFN32)可编程GPIO管脚,支持SPI.UART.I2C.I2S.RMT.TWAI.PWM.电机控制PWM和SDIO。它还集成了12位ADC和温度传感器。 ESP32-C6支持Matter,可用于构建MatteroverWi-Fi终端设备和MatteroverThread实现多系统终端设备,实现多系统.多平台智能家居设备的无缝通信与合作。还可用于构建Thread边界路由器等其他Matter解决方案.Matter网关和Zigbee网桥。 飞睿科技代理商ESP32-C6由乐鑫成熟的物联网开发框架组成ESP-IDF提供软件支持。目前正在开发中的。ESP-IDFv5.1将包含对ESP32-C6的初步支持。ESP-IDF对ESP32-C6的功能支持列表。用户通过乐心ESP-AT和ESP-HostedSDK,可将ESP32-C6用作外部主机的协处理器。ESP32-C66还支持乐信构建AIOT产品的完整云平台方案 ESPRainMaker®。 如您对ESP32-C6系列产品感兴趣,请联系我们的客户支持团队。 乐鑫近期发布了 ESP-IDFv5.0,对ESP-IDFv4.x重大更新,这是目前新的稳定版。v5.0版本可以和大多数一起使用v4.x版本构建的应用程序兼容性也进行了一些非兼容性更新,并删除了一些废弃的功能。用户在更新项目时需要相应地修改代码。 ESP-IDFv5.0的新特征包括: 支持:ESP32-C2和ESP32-H2SoC;对其他ESP32SoC(ESP32-S2.ESP32-S3和ESP32-C3)扩展支持;安全功能包括OTA升级期间预加密固件的分发、更安全的Wi-Fi新增配网系统Wi-Fi支持快速Station切换的802.11r,SoftAP在Station模式下进行WPS注册和WPS注册WPA3SAEH2E。 v5.0版本还进行了一系列的bug修复,比如ESP32-C3和ESP32-S3部件上的电子保险丝问题,使用RTC时的上电复位问题,降低了一些应用的功耗,修复了ESP32-S3睡眠模式下的某些电源参数。 然而,当你将项目从旧版本迁移到ESP-IDFv5.0点,还需要仔细考虑新版本的一系列非兼容性更新,如更新蓝牙操作的应用程序编程界面(API)、构建系统、网络(包括从OpenSSL到mbedTLS或esp-tls加密),删除旧的ADC驱动程序,不再对Python3.6提供支持。 目前正在开发中ESP-IDFv5.1将包含对飞睿科技代理商乐鑫ESP32-C6 初步支持。
查看详情 查看详情
上一页
1
2
...
102

地址:深圳市宝安区西乡街道麻布社区宝安互联网产业基地A区6栋7栋7706

邮箱:Sales@ferry-semi.com

版权所有©2020  深圳市飞睿科技有限公司  粤ICP备2020098907号    飞睿科技微波雷达wifi模块网站地图